2.

Analog layout design

Kanazawa University
Microelectronics Research Lab.
Akio Kitagawa

Well structures
n-well

n-well process

p substrate
p-well

p-well process

n substrate
n-well

p-well

p- or n- substrate
n-well

p-well
n-well
p- substrate

Twin-well process
(The impurity concentration is
optimized.)

Triple-well process
(The wells can be electrically
isolated each other.)
2

Deep n-well (Triple-well process)

Triple well process

Twin-well process

active
(MOSFET)

active
(MOSFET)

n-well
deep n-well

n-well

retrograde p-well
active
FOX

n-well

p
n-well
deep n-well
p-substrate

active
FOX

FOX

n-well

FOX

p-substrate

Shallow trench isolation (STI)

SiO2

Field

Active

Field

Active

Field

isolation

MOSFET

isolation

MOSFET

isolation

FOX

GOX

FOX

GOX

VDD cannot invert the MOS interface.

FOX

Si

FOX: Field Oxide (Thickness = 100nm)

GOX: Gate Oxide (Thickness = several nm)

Layout and cross section (Twin

well)
poly (G)
contact
S

poly (G)
D

Contact

Wp

Wn

n-active

p-active

p-active

n-active

Ln

Field Oxide
FOX p+

n+

Lp

D contact
D

n+

n-well

FOX

n+

p+
n-well

D
D

p+

FOX

p-substrate

n-ch MOSFET

p-ch MOSFET
5

Layout and cross section (Triple well)

contact poly (G)
S

Contact

poly (G)

Wp

Wn

p-active

n-active

p-active

n-active

Ln

Field Oxide
FOX p+

n+

Lp

D contact
D

n+

deep n-well

n-ch MOSFET

FOX

n+

p+
n-well

n-well

D
D

p+

FOX

p-substrate

p-ch MOSFET
6

Layers

Legend of layers
n-well

Layer numbers are assigned to Well,

Active, Poly, Contact, Metal, Via, Silicide
Protect, and Dummy, respectively.
Some layer is automatically generated
from the pattern on the drawn layer.
ex. FOX and GOX is generated from the
pattern on the active layer.
poly layer

n+
p-sub

Layout

n-active layer

poly
p+
p+
n-well

Cross section

n-active (n+)

p-active (p+)
poly
contact
metal-1
via-1
metal-2
metal-2 layer
via layer
metal-1layer
contact layer
FOX
p-active layer
n-well layer
7

Design Rules

Semiconductor foundry allows the designers to design only the layout

pattern on the top view.
The thickness of layers are fixed by the semiconductor foundry.

The designers have to design the layout according to design rules which
is fixed for each technology. The purpose of design rule is as follows.
Warranty of dimensional precision in micro fabrication
Warranty of precision on electrical characteristics
Prevention of latch-up(NOTE) triggered by parasitic bipolar-transistors

Design rule violation is automatically detected and reported in DRC

(Design Rule Check).
A semiconductor company accepts only the design that is passed the
specified design rules.
NOTE: Latch-up
The inadvertent creation of a low-impedance path between the power supply rails
of a CMOS circuit, triggering a parasitic pnpn or npnp structure.
8

Example of design rules (1)

Geometry Rules
n-well
p-active
poly-1
2

contact

Metal-1

1
1

2
1

Via-1

poly rule

active (p+, n+) rule

metal-1 rule

min. width = 2
min. spacing 2

min. width = 2
min. spacing to well = 2 (inside)
min. spacing to well = 1 (outside)
min. spacing to poly = 1

min. width = 2
min. spacing = 2
min. extension beyond contact = 1
min. extension beyond via-1 = 1
9

Example of design rules (2)

Minimum Density Rules

Antenna Rules
(Process-Induced Damage Rules)

Fine featured processes utilize

CMP (Chemical-Mechanical
Polishing) to achieve planarity.
Effective CMP requires that the
variations in feature density on
a layer be restricted.

The "Antenna Rules" deal with process

induced gate oxide damage caused when
exposed poly-silicon and metal structures,
connected to a thin oxide transistor, collect
charge from the processing environment (e.g.,
reactive ion etch) and develop potentials
sufficiently large to cause Fowler Nordheim
current to flow through the thin oxide. The
rules require that the area of the polysilicon
and metal over field oxide divided by the area
of the transistor gate (thin oxide area) must be
less than Np (where Np is a limit that depends
on the process and on design targets).

SF(poly)
SF(M1)

SG

10

Verifications of the layout design

DRC (Design Rule Check)
Detection of the design rule violation

ERC (Electrical Rule Check)

Detection of the open/short error

LVS (Layout VS Schematic)

Equivalence checking between layout and
schematic
The layout design checker has a batch processing mode and
interactive mode.
11

Influence on circuit performance of

the layout
Frequency response in high-frequency region
The parasitic resistance and the parasitic capacitance raise an
unintended pole and zero.
The long interconnect acts as a parasitic inductor or LC resonator.

Precision of the circuit operation

Common centroid layout of MOSFET, C, and R can improve the
production tolerance and mismatch.
Symmetric layout of interconnect can improves the production
tolerance and skew of the digital signal (delay) and analog signal
(phase lag).

Noise and jitter characteristics

The parasitic resistance, especially poly-Si, act as a thermal noise
source.
The parallel placement of interconnect raise a crosstalk of signals. 12

(1) Layout of the MOSFET

13

Layout sample of MOSFET

n-well

p-ch

n-ch

n-active (n+)

p-active (p+)
poly
contact

metal-1
via-1
metal-2

B
14

Parasitic of MOSFET
Parasitic
Long W
LD

LS

S
B

Drain junction

D capacitance

C j W LD
G

RG R

W
L CgsWL

C j W LS

Gate resistance
S
(R: sheet
Gate-Source capacitance
resistance)

Long W: large time constant of gate poly-Si

Long W: large thermal noise of gate poly-Si
Long LD, LS: large parasitic capacitance and resistance of drain/source area
Few number of contact: Shift or fluctuation of substrate potential
How can you design the MOSFET with larger W?
15

Fingered MOSFET
MOFET should be
sectioned to reduce
the gate resistance.

W/4

High-performance MOSFET array

W
1
R

L
gm
gm: trans-conductance

g m y21

dI ds
dVgs

This condition is
often met in the case
of W/L < 20.
W/L < 10 is
recommended.

Finger
Abutment
G

S
D

B
Multiply = 4 (W/4 4)

16

Reduction of the drain junction

capacitance (single MOSFET)
D Abutment
G
S

LD

S
LD

D
S

W
W/2

C DB C jWLD

>

C DB

W
C j LD
2

Cj = Capacitance of drain bottom pn junction per area (F/m2)

17

Reduction of the drain junction

capacitance (series MOSFET)
D
LD

Abutment

D/S

SLGmin

LD

C p 2C jWLD

>

C p C jWSLG min

Cj = Capacitance of drain bottom pn junction per area (F/m2)

SLGmin = minimum gate spacing

18

Dummy gate
The dummy pattern may be formed to reduce the production tolerance.
G
D

Dummy gate

Dummy gate

19

Interdigitated body contact

The body/well contact may be added to immobilize the
substrate/well potential in the very large MOSFET.
G
D

S
20

IN1 IN2 OUT

VDD

Layout of logic gate

High area utilization

Constant height of all cell
Horizontal runs of metal are used to
supply power (Rail), and vertical runs
of metal (or poly) are used to input
and to output the signals.

2NAND

Outline box of the cell

poly-1

n-well

n+

Metal-1

p+

Metal-2

Contact

Via-1

VSS

21

Matching layout
Matching layout is used to enhances the relative
precision of device pair (e.g. a differential pair, a
current mirror). (around 1%)
Use of The repeat of warp of the fundamental unit
The devices of the different shape and direction match very
poorly.

Use of the dummy pattern

Use of the common centroid pattern

Trimming is necessary if you expect more precise

matching.(less than 0.1%)
22

Distribution of GOX thickness

Flux of O2
G

Temperature and flow

distribution in the oxidation
furnace

GOX
n+
S

n+
D

FOX

GOX
n+
S

n+

FOX

Distribution of GOX thickness

Fluctuation of Vth and Ids
several %
23

Common centroid layout

The fluctuation of the device characteristics may be
canceled using the common centroid.
1.
2.
3.

The centroid of the matched devices should coincident.

The array should be symmetric around both the x and y-axis.
Each matched device should consist of an equal number of segments
oriented in either direction.

A B B A

A B

A B B A

A B B A

4 segments

B A

B A A B

B A A B

4 segments

8 segments

A B B A
B A A B
16 segments24

Segmentation and Placement for

common centroid layout
W/2

MOSFET A
W

Dummy

Dummy

D
Matched
devices
MOSFET B

D
GA

S
GB

GA
D

D
Dummy

Distribution of device parameter

GB

Dummy

25

Layout sample of a differential pair

VSS

D2

D1

VSS

D2

Dummy

Dummy
G2

S12

G1

poly-1

Metal-1

n+

Metal-2

p+

Via-1

Contact

S12

G2

D1

D2

G1

G2
VSS

S12

26

(2) Layout of the passive devices

27

Example of the characteristics of

the passive device
Component

Values

Mismatch Temp.
Coefficient

Volt.
Coefficient

MOS Cap.

2.2 2.7
fF/m2

0.05%

50 ppm/

50 ppm/V

Poly2/Poly1
Cap.

0.8 1.0 fF/

m2

0.05%

50 ppm/

50 ppm/V

p+ Resister

80 150 /

0.4%

1500 ppm/

200 ppm/V

p+ diff. Resistor 50 80 /

0.4%

1500 ppm/

200 ppm/V

Poly Resistor

20 40 /

0.4%

1500 ppm/

100 ppm/V

N-well Resister

1 k 2k /

1%

8000 ppm/

10k ppm/V

The mismatch error on a chip is very small.

28

Structure of MIM capacitor

Poly Capacitor (Before 0.25m CMOS process)
MIM Capacitor (After 0.18m CMOS process)
VDD
(Shield)

VDD
(Shield)

Capacitor Metal

Poly-2
Poly-1
N+

FOX(SiO2

Metal-x+1

N+

Metal-x
FOX(SiO2

N-well

N-well

P-substrate

P-substrate

Poly Capacitor

MIM Capacitor
29

Layout sample of a MIM capacitor

Metal-5

Metal-4

Dummy CM

CMIM
Cp

Device model with parasitic

CM

Metal-4
Capacitor Metal (CM)
Metal-5

MIM Capacitor with the dummy CM

VIA4
Dummy (The dummy metal is automatically inserted, if the dummy is not
specify. The dummy metal may work as a parasitic capacitance.) 30

Structure of spiral inductor

Metal-4

CP

Top metal
Metal-1
Slit (prevent the
induction current)
Top

Top Metal

RS

CF

Device model with the parasitic

Top metal or dedicated layer for
inductor is used.

VIA4

M4
M1 VSS
(Shield)

CF

FOX(SiO2)

The inductor is dissipative in the

chip area.

Substrate

Cross section
31

Structure of the resistance

Active
Protect

M1

VDD
(Shield)

Active
M1
FOX

P+
N-well

N+

Silicide

p+ resistor

VDD
(Shield)

FOX

N+
N-well

P-substrate

M1

Active

P-substrate

n-well resistor

Poly
FOX

N+
N-well
P-substrate

poly resistor

32

Layout sample of a poly resistor

L
(recommended L/W > 5)
W
RS : SheetResistance
R RS

Device model with the parasitic

poly

Metal-1

W
L
Protect (non-silicide area)

p-select, n-select or high-resistance

33

Common centroid layout of a

resistor pair
Dummy

R
R
R2

R2

Metal-1

p+ diffusion

Dummy
34

(3) Shielding and guard ring

35

Type of noise
Inherent noise
Noise resulting from the discrete and random movement of charge
in a device
Thermal noise, Flicker noise, shot noise
The noise floor depends on the circuit design quality

Quantization noise
Noise resulting from the finite digital word size
The SNR (signal-to-noise ratio) depends on the accuracy of ADC
and DAC.

Coupled noise (Crosstalk)

Noise resulting from the signals adjacent circuits deeding into each
other
The noise immunity depends on a layout.
36

Type of coupled noise

Circuit model

Electromagnetic model
Capacitive coupling
Inductive coupling
Substrate current

Parasitic capacitance
Parasitic inductance
Parasitic resistance

37

Capacitive coupling
Analog circuit
Vdig

Digital signal

Cc
Vanalog

Analog signal

Analog circuit

Vsig

Rout

Cs

Vsig
1
SNR
j Cc Rout Vdig

38

Shielding of interconnects
Shielding plate

Shielding line
Signal

Analog circuit

Digital circuit

Digital line
3W

GND

p-substrate

p-substrate

Analog line
analog VSS

39

Shielding of substrate
Analog signal
Digital signal

Capacitor

VDD

VDD

FOX
n+

Shield
Noise
(charge and discharge)

Shield

FOX
n+

n-well
p-substrate

Cross section
40

(termination of
electric field)

Guard ring

(absorption of
minority carrier)

n-guard ring

p-guard ring

Digital circuit
(noise source)

Analog circuit

analog VSS

p-substrate
digital VDD digital VSS

41

Inductive coupling
Analog circuit
Magnetic flux
S
I2(t)

GND
I2(t)

I1(t)
Digital signal current

The induction noise is in

proportion to the loop area S
of the signal and power line.

Current

I1(t)
t
42

Translational symmetric layout

(In-phase circuit)

magnetic flux

magnetic flux
Analog circuit

Analog circuit

VDD

VSS

The translational symmetry reduces

induced current.

VDD

VSS

The mirror symmetry intensifies

the induced current.

43

Pin assignment
The analog input should be arranged in a perpendicular
direction on digital output and the power supply pin.
Vin

Analog Circuit

VDD
Adjacent placement
VSS
Increase the distance

Vout

Digital Circuit

VDD
Adjacent placement
VSS

44

Bypass capacitors on VDD, VSS

lines
p-substrateVSS

VDD

The noise in the VDD, VSS line is

bypassed through the bypass capacitors.

Small MOS capacitors

under the power line.
45

(4) ESD (Electrostatic Discharge)

Protection

46

Input Pad with ESD protection

The ESD protection is required to prevent the damage of the GOX of
a MOSFET from the static charge buildup.
VSS
Input
Pad

Input Pad

VDD

VDD
CMOS
Circuit
VSS

Schematic

FOX

p+

n+

FOX

n-well

p-substrate

Cross section

NOTE: If the inductive load is used the output, the amplitude of the output
signal is larger than power supply voltage. In this case, the ESD protection
diode must be connected tandemly.

47

Layout sample of pad ESD protection

Pad
Layer
n-well
n-active (n+)

p-active (p+)
poly-1
contact
metal-1
via-1
metal-2

VDD
VSS
Input

48