Labs - Digital Logic Design Manual

Lab Manual, Digital Logic Design
Exp # 1.
FAMILIARIZATION WITH DIGITAL LOGIC TRAINER

Logic Trainer is a device which is used to study interaction of different logic and universal
gates.
Figure 1: NB-09 Digital Logic Trainer
Complete description of NB-09 Digital Logic Trainer shown in figure 1 is described below
A
Section A comprises of DC Jack for the power supply adaptor.
B
Section B consists of 8 BIT LED OUTPUT INDICATOR . The bulb in this section glows
when there is logic 1 and remains off when there is logic 0.
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------Digital System Lab,CPED, UET Taxila
1
D
Section D consists of AND GATES. It is a basic combinational logic device where all
inputs must b high for the output to be high.
E
Section E comprises of OR GATES It is a basic combination logic device where the
output goes high when any or two input will be high.
F
Section F consists of NAND GATES. It is a basic combinational logic device where all
inputs must be high for output to be low. It is invert of AND GATE.
G
Section G consists of NOR GATES it is a basic combinational logic device where all
inputs must be low for output to be high. A NOT OR circuit. It is invert of OR. Its
meaning No OR.
H
Section H consists of XOR GATES it is basic combinational logic device where an odd
number of high inputs generates a high output.
I
Section I consists of NOT GATES it is a basic combinational logic device where the
output is always the opposite from the input. It is also called an inverter.
J
Section J consists of VOLTAGE SECTION one port is of +5V, the other is for ground
connection and the third is of -5V.
Also Section J consists of VOLTAGE SECTION one port is of +15V, the other is for
ground connection and the third is of -15V.
L
Section L consists of PULSE. It can be generator a pulse of 1 second, 0.1 second and 0.01
second.
M
Section M consists of DATA SWITCHES. There are five data switches in this trainer and
have four there test point in their correspondence.
N
Section N consists of SOLDER LESS BREADBOARD OR PROTO BOARD It is
consisting of so many holes.

2
Exp # 2.
VERIFICATION OF TRUTH TABLE OF BASIC LOGIC

GATES
Apparatus: 7408ICs, Logic Trainer and connecting wires.
OBJECTIVE
The basic logic gates are the basic building blocks of more complex logic circuits. The purpose
of this lab is to learn about Digital Logic and digital logic circuits. By the end of
this lab you will have an understanding of the functions and operations of different logic gates.
THEORY
AND Gate
The AND function is similar to the multiplication in mathematics. This is the all or nothing
operator and it provides a logic 1 output only when all the inputs of the gate are at logic 1, and
logic 0 output for all other input combinations. The AND function is described in terms of the
following truth table.
Figure 2 input AND Gate.
+V cc
14
13
1
12
7408
3
4
4
11
5
6
A
0
0
1
1
Truth Table of AND Gates

i/ps
o/p
B
G1 G2 G3
0
1
0
1
G4
10
2
9
3
8
7
G ro u n d
+Vcc
Comments: _____________________________________
________________________________________________
________________________________________________

3
Exp # 3.
VERIFICATION OF TRUTH TABLE OF BASIC LOGIC
GATES
Apparatus: 7432 ,7404,7402 ICs, Logic Trainer and connecting wires.
OBJECTIVE
The basic logic gates are the basic building blocks of more complex logic circuits. The
purpose of this lab is to learn about Digital Logic and digital logic circuits. By the end of
this lab you will have an understanding of the functions and operations of different logic
gates.
OR Gate
The OR function is similar to the mathematical function of addition and the output for the
OR gate may be analyzed using the laws of addition. The logic operator for the OR
function is a + sign. The output will be logic 0 only if all the inputs are logic 0, and the
output will be logic 1 anytime any input is at logic 1. Here, OUT = A+B.
Figure 2 input OR Gate.
1
2
1
7432
3
4
5
6
7
G ro u n d
A
0
0
1
1
14
Truth
Table of OR Gates
i/ps1 3
o/p
B
G1 G2 G3
12
0
11
1
0
10
1
G4
1
9
3
Comments: ______________________________________
_________________________________________________
_________________________________________________
NOT Gate
The NOT circuit or inverter performs the basic logic function of complementation. It may be
identified by the presence of a bubble on the input or the output of the traditional logic symbol.
The output of NOT gate is the inverse of the input. Unlike the others it only has one input and
one output.
Figure 1 input NOT Gate
4
0
0
0
1
+Vcc
Truth Table of NOT Gates.
14
1
13
i/ps
A
0
1
12
7404
11
5
o/p
G1
G2
G3
G4
10
3
Comments: ___________________________________
7
G ro u n d
_____________________________________________
_____________________________________________
NAND Gate
The NAND function is the complement of the AND function and the logic symbols have
the inversion on the output. NAND gate is constructed by adding an inverter after
AND operator. The NAND function provides logic 0 on the output only when both inputs are
logic 1, and logic 1 output for all other combinations. Here, OUT = B A.
Figure: 2-input NAND gate
+V cc
1
2
3
13
1
12
7400
5
6
7
G ro u n d
Truth Table of NAND Gates
14
11
10
9
3
i/ps
A
0
0
1
1
o/p
B
0
1
0
1
G1
G2
G3
G4
Comments: _____________________________________
_______________________________________________
_______________________________________________
NOR Gate
The complement of the OR function is the NOR function and the logic symbol has the
inversion present on the output. NOR gate is constructed by adding an inverter after OR
operator. Here, OUT = B A + .
Figure: 2-input NOR gate

5
+V cc
1
14
13
4
12
7402
11
10
3
6
7
G ro u n d
A
0
0
1
1
Truth Table of NOR Gates

i/ps
o/p
B
G1 G2 G3
0
1
0
1
G4
Comments: __________________________________
____________________________________________
____________________________________________
PROCEDURE
Place the IC 7408LS on the trainer board.
Connect VCC and ground to the respective pins on the trainer board.
Connect the inputs to the input switches provided in the trainer board.
Connect the outputs to the switches of output LEDs.
Apply various combinations of inputs as shown in the truth table and observe the
conditions of LEDs.
Similarly follow these steps for other gates.
PROBLEMS
Measure the output voltages in all cases.
What is the difference between a Inverter and a NOT gate?
Lab Exercise:
1. Students are required to verify the functioning of each gate in each of there ICs through
T.Ts.
2. Then the gate, which is not functioning properly, should be clearly indicated.

6
Exp # 4
IMPLEMENTATION OF MULTIVARIABLE BOOLEAN

EXPRESSION USING LOGIC GATES.
Apparatus: 7408, 7432, 7404 ICs, logic kit and connecting wires.
OBJECTIVE
Boolean algebra uses many of the same laws as those of ordinary algebra. In this experiment,
well know about this laws & theorem.
THEORY
Generally youll find that the basic logic functions AND, OR, NAND, NOR, and NOT are not
sufficient to implement complex digital logic functions. These gates are the basis for building
more complex logic circuits that are constructed using various combinations of gates which is
known as Combinational Logic. Combinational logic requires the use of two or more gates to
form a useful, complex function. These complex functions usually begin as a Boolean Equation
and the logic circuit may be implemented directly from this equation. The Boolean laws and
rules are shown below:
Given Boolean function is
F1 = a b c + .a b c
F2 = (a + b+ c) (a + b)
a
a . b '. c
a'
b'
c'
a .b '
F 1 = a . b '. c + a '. b . c
To LE D
a '. b
a '. b . c
a+b
a+b+c'
F 2 = ( a + b + c ) ( a '+ b )
a '+ b
To LED

7
Now we shall check the logic circuit by the following Truth Table.
Truth Table
o/ps
i/ps
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
F1
c
0
1
0
1
0
1
0
1
Actual
Observed
F2
Actual
Observed
Comments: _______________________________________________________
_________________________________________________________________
_________________________________________________________________
_________________________________________________________________
Lab Exercise:
1.
2.
Students are directed to write F1and F2 in terms of NAND and NOR gates only.
Then implement F1 & F2 with universal gates and verify your result.
Comments: __________________________________________________________________________
____________________________________________________________________________________
____________________________________________________________________________________
____________________________________________________________________________________
____________________________________________________________________________________
____________________________________________________________________________________
____________________________________________________________________________________

8
Exp # 5.
VERIFICATION OF DEMORGANS THEOREM

Apparatus: 7408, 7432, 7404 digital logic kit and connecting leads.
OBJECTIVE
De Morganstheorem allows for the simplification of a Boolean Expression by the cancellation
of some redundant inversions. In this experiment, well know about this laws & theorem.
DE MORGAN`S THEOREM
De Morgan developed a theorem that allows conversion between logic expressions that has
inversions on the output to a different logic expression with the inversions on each of the
inputs. This may allow for the simplification of a Boolean Expression by the cancellation of
some redundant inversions. There are two Boolean Equations that represent De Morgan's
Theorem:
It has two statements.
1.
2.
(x+y+z) = x.y.z
where let F1 = (x+y+z) & F2 = x.y.z
(x.y.z) = x+y+z
where let F3 = (x.y.z) F4 = x+y+z
x'
x '.y '
y'
F 2 = x '. y '. z '

(T o L E D )
z'
x
x+y
y
x+y+z
F 1 = (x + y + z )'
(T o L E D )
z
x'
x '+ y '
y'
F 4 = x '+ y '+ z '

(T o L E D )
z'
x
x .y
y
F 3 = (x .y .z )'
z
(T o L E D )

9
Now we shall check this logic circuit by the Truth Table.

Truth Table
i/ps
x
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
F1 = (x+y+z)
Actua Observ
l
ed
o/ps
F2 = x.y.z
F3 = (x.y.z)
Actu Observ Actu Obser
al
ed
al
ved
F4 =x+y+z
Actu Obser
al
ved
Comments: __________________________________________________________________________
____________________________________________________________________________________
____________________________________________________________________________________
____________________________________________________________________________________
____________________________________________________________________________________
____________________________________________________________________________________
____________________________________________________________________________________
PROCEDURE
1. At first construct the circuits shown in the Boolean laws.
2. Check if the laws are valid. Give truth tables for each law.
3. Construct the circuits shown in the circuit diagram.
4. Check if the two circuits give the same result.
OBSERVATIONS & RESULTS
1. Write truth tables for each Boolean law.
2. Write the equation for the figure 1. Now try to simplify it and find the equation for
figure 2 from it.

10
Lab. Exercise:
Students are directed
1.
To write F1, F2, F3 and F4 in terms of NAND and NOR gates only.
2.
Then implement F1, F2, F3 and F4 with Universal gates and verify your result.
Comments: ________________________________________________________________________
___________________________________________________________________________________
___________________________________________________________________________________
___________________________________________________________________________________
___________________________________________________________________________________
___________________________________________________________________________________
_

11
Exp # 6.
TO REALIZE HALF & FULL ADDER USING BASIC LOGIC GATES.

Apparatus: 7486, 7432, 7408, 7404 ICs, logic kit and connecting leads.
OBJECTIVE
Digital computers perform a variety of information-processing tasks. Among the basic
functions encountered are the various arithmetic operations. The most basic arithmetic
operation is the addition of two binary digits. In this experiment well know about the circuits
that will add binary digits.
THEORY
Half Adder:
Half Adder is combinational logic circuit that generates the sum of two binary numbers (each
having 1 bit length). The logic circuit has two inputs and two outputs i.e. Sum & Carry
abbreviated as SHA & CHA respectively.
First of all, we shall construct Truth Table of Half Adder
Truth Table
i/ps
o/ps
0
0
1
1
0
1
0
1
SHA = xy+xy
Actual Observe
d
CHA = x y
Actua Observ
l
ed
Now we write Boolean function from above Truth Table as

SHA =xy + xy
CHA = xy
Implementation
Now we implement above Boolean expression by basic logic gates i.e.

12
HA
= x + y
(T o L E D )
HA
=x y
(T o L E D )
Now we shall check this logic circuit by the Truth Table of Half Adder.

13
Lab Exercise:
1.
Students are required to write outputs of Full adder using Basic logic gates..
2.
Then implement Half Adder using basic logic gates.
Full Adder:
Full Adder is combination logic circuit that performs the sum of 3 input binary numbers, (each
having 1 bit length). Two of the binary input variables are x and y represent the two significant
bits to be added the third input z, represents the carry from previous lower significant position.
Outputs of Full Adder are Sum and Carry represented as SFA and CFA respectively.
First of all, we shall construct Truth Table of Full Adder i.e.
Truth Table
i/ps
x
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
o/ps
SFA
CFA
Actual Observ Actual Observ
ed
ed
Now we write Boolean expression for Sum and Carry of Full Adder.
Sum = xyz+xyz+xyz+xyz
Simplifying by using Boolean Postulates & theorems/k-map, we get
Sum =(xy+xy) . z + (xy+xy).z
SFA = (x y ) z
Carry = xyz + xyz + xyz+xyz
Simplifying by using Boolean Postulates & theorems/k-map, we get
Carry = (xy+xy) . z+xy
CFA = (x y) z + xy
Implementation
Now we implement simplified Boolean expressions of SFA & CFA i.e.

14
z
H A1
H A2
SFA = (x + y) + z
To LED
CFA = (x + y) z + xy
To LED
We shall check this logic circuit by the Truth Table of Full Adder
PROCEDURE
At first connect the circuit shown in the figure 1.
Vary the inputs as shown in the truth table. See if the circuit is true for all the
combinations.
Now connect the circuit as shown in the figure 2.
Vary the inputs as shown in the truth table. See if the circuit gives us the result as shown
in the table.
OBSERVATIONS & RESULTS
Write the Boolean expressions for the figure 1 and find the sum and carry equation from
those expressions (for half-adder).
Repeat step 1 for full- adder (figure 2).
PROBLEM
1. Explain how the logic diagram of Figure 1 performs as a half adder.
2. Explain how the logic diagram of Figure 2 performs as a full adder.
Lab Exercise:
1.
2.
Students are required to write outputs of Full Adder using Basic logic gates.
Then implement output of Full Adder with Basic logic gates.

15
Exp # 7.
IMPLEMENTATION/DESIGN OF MAGNITUDE COMPARATORS
Apparatus: 7486, 7432, 7408, 7404 logic kit and connecting wires.
ONE BIT MAGNITUDE COMPARATOR
One Bit Magnitude Comparator is combination logic circuit which is used to compare two
input binary numbers (each having one bit length) to check weather two inputs are equal or one
less than other or greater then.
First of all we write Truth Table of 1 Bit Magnitude Comparator i.e.
Truth Table
i/ps
x
0
0
1
1
y
0
1
0
1
Ex=y
1
0
0
1
o/ps
Gx>y
0
0
1
0
Lx<y
0
1
0
0
Boolean functions for one bit Magnitude Comparator

E = xy+ xy
G = xy
L = xy
Implementation
To check this logic
circuit, we shall use the
above Truth Table
2 BIT MAGNITUDE
COMPARATOR
Two Bit Magnitude
Comparator which is
used to compare two
input binary numbers
(each having bit length of
two ) to check weather
two inputs are equal or
one less than other or
greater then.
x'
y'
x y
E = ( x y + x ' y ')
(T o L E D )
x' y'
G =x y'
(T o L E D )
L = x' y
(T o L E D )

16
USING XOR GATES AND BASIC LOGIC GATES

First of all we write Truth Table of 2 Bit magnitude Comparator.
Truth Table
i/ps
A
A1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
o/ps
B
A0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
B0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EA=B
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
GA>B
0
0
0
0
1
0
0
0
1
1
0
0
1
1
1
0
LA<B
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0

17
Now we simplify outputs of 2 Bit Magnitude Comparator by k-map technique.

18
k-maps for outputs of 2 Bit Magnitude Comparator.

k-map of E.
E
B1B0
00
1
A1 A0
00
01
11
10
01
11
10
1
1
1
k-map of G
G
A1A0
B1B0
00
01
11
10
00
01
1
1
1
1
1
11
10
k-map of L.
L
A1 A0
B1B0
00
01
11
10
00
01
1
11
1
1
10
1
1
Boolean Functions
Now writing Boolean functions from above k-maps for outputs of two Bit Magnitude
Comparator, we get.
E = A1 A0 B1 B0+ A1 A0 B1 B0+ A1 A0 B1 B0+ A1 A0 B1 B0
E= A1 B1(A0 B0+ A0 B0)
+ A1 B1(A0 B0+ A0 B0)
E = (A0 B0+ A0 B0) (A1 B1+ A1 B1)
E = ( A 0 + B 0 ) '( A 1 + B 1 ) '
G = A1B1+ A1 A0 B1 B0+ A1 A0 B1 B0
G = A1B1 + A0 B0 (A1B1+ A1 B1)
G = A 1 B '1 + A 0 B '0 ( A 1 + B 1 ) '
L = A1B1 + A0 B0 (A1B1+ A1 B1)
19
L = A '1 B 1 + A '0 B 0 ( A 1 + B 1 ) '

20
Implementation
A
E = (A 0 + B 0) (A 1 + B 1)
(T o L E D )
G = A 1 B '1 + A 0 B '0 ( A 1 + B 1 ) '

(T o L E D )
L = A '1 B 1 + A '0 B 0 ( A 1 + B 1 ) '

(T o L E D )
We check this circuit by Truth Table of 2 Bit Magnitude Comparator as written before.

21
Exp # 8.
DESIGN & IMPLEMENTATION OF A 2 x 4 DECODER

Apparatus: 7432, 7408, 7404 ICs logic kit and connecting leads
Decoder :
n 2n.
n = No. of input lines.
2n = No. of outputs of a Decoder.
Decoder is a circuit that convert binary information from n-input lines to max of 2 n
output lines e.g. if we have 2 inputs i.e. x,y then there will be 4 output of a Decoder and
size of Decoder will be 2X4.
d0
d1
d2
d3
2X4
D ECO D ER
output lines
data input lines
Block Diagram of 2X4 Decoder.
Truth Table 2 X 4 Decoder

i/ps
x
0
0
1
1
y
0
1
0
1
Enable
E
1
1
1
1
o/ps
d0
1
0
0
0
d1
0
1
0
0
d2
0
0
1
0
d3
0
0
0
1
Boolean Functions for 2 x 4 Decoder

do = E x y
d1 = E xy
d2 = E x y
d3 = E x y

22
Implementation
x
x'
y'
0 =
x' y'
(T o L E D )
1 =
x' y
(T o L E D )
d2 = x y'
(T o L E D )
d3= x y
(T o L E D )
Now we check this logic circuit by using Truth Tables of 2X4 Decoder as drawn above.
Lab Exercise:
1. Students are directed to write the Truth Table of 3X8 Decoder with Enable.
2. Then, write output Boolean Functions of 3X8 Decoder.
3. Then implement 3X8 Decoder using logic gates.

23
Exp # 9.
DESIGN OF A 2X1 and 4X1 MULTIPLEXER.

Apparatus: 7432,7408,7404 logic kit and connecting wires
Multiplexer
Multiplexer, simply called Mux, is a data selector and is capable of selecting one of
many input lines (usually 2n) and display its input status on the only output line
available.
A Mux has
1.
Select lines
2.
Data input lines
3.
Output line.
Block diagram of 2x1 MUX
I0
2X1 M U X
d a t a i/p lin e s
o u tp u t
I1
S
s e le c t lin e
I0, I1 are inputs of Mux

S is select line
Y is output
The function table of 2x1 Mux is
Select line
S
0
1
o/p
Y
Io
I1
The Boolean function for 2x1 Mux is

Y = I1 s + I0 s

24
Logic Diagram of 2x1 Mux is

I1
I0
I1 s
I1 s + I0 s ' = Y
To LED
s'
I0 s '
Block diagram of 4x1 MUX

I0
d a t a i/ p lin e s
I1
I2
I3
4X1 M U X
Y
o u tp u t
s e le c t lin e s
I0, I1,I2 and I3 are inputs of Mux

S1 and S0 are select lines
Y is output
The function table of 4x1 Mux is
Select
lines
S1
S0
0
0
0
1
1
0
1
1
o/p
Y
Io
I1
I2
I3
.
The Boolean function for 4x1 Mux is
Y = I0 S1 S0+ S1 S0 I1+ S1 S0 I2+ S1 S0I3

25
Logic Diagram of 4x1 Mux is

S
I0
I0
I1
I1
I2
I2
I3
I3
Y
To LED
We check this logic circuit by Function Table of 4X1 Mux as drawn above.

26
Exp # 10.
IMPLEMENTATION OF FULL ADDER USING MUX

Apparatus: 74151 MUX, connecting wires.
MUX :
2n 1.
n = No. of select lines.
2n = No. of inputs of MUX
if n = 3, size of MUX is 8x1 i.e.
Data input lines
I0
I1
I2
I3
I4
I5
I6
I7
8X1 M U X
Y
o u tp u t
s e le c t lin e s
Function Table
x
0
0
0
0
1
1
1
1
Select lines
y
0
0
1
1
0
0
1
1
z
0
1
0
1
0
1
0
1
o/p
Y
Io
I1
I2
I3
I4
I5
I6
I7
Pin Configuration of 74151 MUX

27
I1
I0
7
8
E
G ND
I4
I5
I6
I7
x
y
z
16
15
14
13
Data i/p
lines
VCC
12
11
10
9
Data select
lines
o/p lines
Data i/p
lines
I3
I2
74LS151
7 4 L S 1 5 1 in v o lv e s 8 X 1 m u x .

28
Truth Table of Full Adder

i/ps of Full Adder
x
y
z
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
o/ps
S
0
1
1
0
1
0
0
1
C
0
0
0
1
0
1
1
1
Function Table of 8x1 Mux

i/p of Full Adder = Select lines
of MUX
x
y
z
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
o/p of 8x1
mux
S=Y
0
1
1
0
1
0
0
1
o/p of 8x1
mux
C=Y
0
0
0
1
0
1
1
1
o/p of 8x1
mux
I0
I1
I2
I3
I4
I5
I6
I7
Procedure:
First of all we check/implement Carry of Full Adder (having 3 inputs) using 8X1 Mux, for this
take :
I0 = 0, I1 = 0, I2 = 0, I3 = 1, I4 = 0, I5 = 1, I6 = 1, I7 = 1, from Carry column of Truth table of Full
Adder and then select x,y,z from Function table of 8X1 Mux and then observe outputs at Y Pin
of 74151 IC, that should be equal to Carry of Full Adder for combination of x,y,z at select
lines, which is inserted through data switches, this step is repeated for all x,y,z combinations, at
select lines to observe Carry of Full Adder.
Then we check/implement Sum of Full Adder for 3 input variables, using 8X1 Mux for this, we
take :
I0 = 0, I1 = 1, I2 = 1, I3 = 0, I4 = 1, I5 = 0, I6 = 0, I7 = 1, from Sum column of Truth Table of Full
Adder, as data inputs to 8X1 Mux, and then for each combination of x,y,z at select lines from
Function table. We see output at Y Pin of 74151 IC, which should be equal to value of Sum of
29
Full Adder for x,y,z combination at select lines, which is inserted through data switches, this
step is repeated for all x,y,z combinations, at select lines to observe Sum of Full Adder.

30
Exp # 11
IMPLEMENTATION OF FULL ADDER WITH 2, 2X4 DECODERS

Apparatus: 74139, 7400 ICs and connecting wires
Decoder :
n 2n.
n = No. of input lines.
2n = No. of outputs of a Decoder.
Decoder is a circuit that convert binary information from n-input lines to max of 2 n
output lines e.g. if we have 2 inputs i.e. x,y then there will be 4 output of a Decoder and
size of Decoder will be 2x4.
2X4
D ECO D ER
d0
d1
d2
d3
output lines
data input lines
Block Diagram of 2X4 Decoder.
Truth Table of 2X4 Decoder

x
0
0
1
1
y
0
1
0
1
E
1
1
1
1
d0
1
0
0
0
d1
0
1
0
0
d2
0
0
1
0
d3
0
0
0
1
Boolean Functions for 2 x 4 Decoder

do = E x y
d1 = E xy
d2 = E x y
d3 = E x y
Implementation

31
y'
x'
0 =
x' y'
(T o L E D )
1 =
x' y
(T o L E D )
d 2= x y'
(T o L E D )
d 3= x y
(T o L E D )
Now we implement Half Adder with 2x4 Decoder.

Truth Table of Half Adder
i/ps
x
0
0
1
1
o/ps
y
0
1
0
1
SHA
0
1
1
0
CHA
0
0
0
1
Truth Table of 2X4 Decoder

i/ps
x
0
0
1
1
o/ps
y
0
1
0
1
d0
1
0
0
0
d1
0
1
0
0
d2
0
0
1
0
d3
0
0
0
1
By comparing Truth Tables of half Adder and 2 X 4 Decoder.

We can see that
SHA = d1 + d2
CHA= d3
Block Diagram of Half Adder with Truth Table of 2X4 Decoder

32
do
open
x
d1
2X4
DECODER
y
HA
d2
d3
HA
Note:
By connecting an OR gate with output Pin 1 & 2 of 2X4 Decoder. Half Adder can be
implemented with 2X4 decoder. Similarly by connecting two Half Adders, we can form a Full
Adder by using 2, 2X4 Decoder ICs.
Truth Table of Full Adder
i/ps
Y
0
0
1
1
0
0
1
1
x
0
0
0
0
1
1
1
1
o/ps
z
0
1
0
1
0
1
0
1
SHA
0
1
1
0
1
0
0
1
CHA
0
0
0
1
0
1
1
1
Block Diagram of Full Adder with 2, 2X4 Decoders.

Using the concept of implementation of Half Adder with 2X4 Decoder, we can implement Full
Adder with 2, 2 X 4 Decoders.
d
open
2X4
DECO DER
H A
=x+y
2X4
DECODER
open
FA
=x+y+z
FA
H A
FA
Pin Configuration of 74LS139

33
VC C
16
15
open
H A
=x+y
d3
G N D
H A
14
13
d
d
d
d
0
1
2
3
12
= x+y
z
open
Data o/p
lines
+5 V
Data i/p
lines
Data i/p
lines
data
o/p lines
d
d
74LS139
11
10
9
(C
x+y+z
)'
C
(C
x+y
FA
=x+y+z
FA
)'
P in C o n fig u r a tio n o f 7 4 L S 1 3 9 (2 , 2 X 4 D E C O D E R )

34
EXP NO.12
VERIFICATION OF DIFFERENT TYPES OF FLIP FLOPS
APPARATUS
IC 7476, IC 7400,IC 7404
OBJECTIVE
The aim of this experiment is to study the fundamentals of basic memory units and to become
familiar with various types of flip-flops. Well verify the Truth tables of Flip-Flops:
RS-Type
D- Type
T- Type.
JK-Type
THEORY
RS flip-flop is also called Synchronous flip-flop. That means that this flip-flop is concerned
with time. Digital circuits can have a concept of time using a clock signal. The clock signal
simply goes from low-to-high and high-to-low in a short period of time.
Fig. 1 RS Flip Flop and its Truth Table

In case of D flip-flop, The Q output always takes on the state of the D input at the moment of a
rising clock edge. (or falling edge if the clock input is active low). It is called the D flip-flop for
this reason, since the output takes the value of the D input or Data input, and Delays it by one
clock count. The D flip-flop can be interpreted as a primitive memory cell, zero-order hold, or
delay line.

35
In case of T flip-flop, if the T input is high, the T flip-flop changes state ("toggles") whenever
the clock input is strobed. If the T input is low, the flip-flop holds the previous value. The truth
table is as follows:
The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the
S = R = 1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K = 0 is
a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop;
and the combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to the
logical complement of its current value.
36
PROCEDURE
Make connections as shown in the diagrams.
Verify the truth tables for various combinations of inputs.
PROBLEM
Draw a 1- to- 4 line multiplexer using basic gates.
Write the truth table for it.

37
LAB TEST (WEEK 13)

38
Exp No. 14
FAMILIARITY WITH VERILOG HDL

Objectives:
A. Become familiar to Verilog environment.
B. Use at least 2 levels of abstraction in your Verilog code.
C. Write your own Verilog code in the lab
D. Submit the lab report along with the answers of given questions.
PreLab:
This lab describes a hardware description language (HDL).A hardware description language is
a language that describes hardware of a digital system, in a textual form. It can be used to
represent logical diagrams, Boolean expressions and other complex digital circuits. The
language contents can be stored and retrieved easily and can be processed by computer
software in an efficient manner. Two major applications of this language are:
1. LOGICAL SIMULATION
2. SYNTHESIS
Logical simulation
It is the representation of the structure and behavior of a digital logical system through the use
of a computer. The code that tests the functionalities of the design is called Stimulus or Test
Bench.
Synthesis
Logical synthesis is the process of driving a list of components and their interconnections
(called a NETLIST) from the module of a digital system in HDL.
Levels of abstraction in Verilog
The level of abstraction to describe a module can be changes without any change in the
environment there are four levels of abstraction:
Behavioral Level
Dataflow Level
Gate Level
Switch Level
39
What is a Module?
A module is the basic building block in Verilog. A module can b element of a collection of
lower level design blocks.
In Verilog, a module is declared by keyword module a corresponding end module must appear
at the end of the module definition.
Register Transfer Level
Verilog allows the designer to mix and match all four levels of abstraction in a design. In the
digital design community, the term register transfer level (RTL) is frequently used for a
Verilog description that uses a combination of behavioral and data flow constructs and is
acceptable to a logical synthesis tool.
Post Lab:
Answer 5 questions in this lab and submit then in your lab report.
Lab Work:
Verilog Code For simple two inputs AND Gate.
input A
Output
input B
Gate Level Verilog Code:

module and_gate (Out, A, B); //Starting of module and defining inputs and outputs
input A, B;
//inputs
output Out;
//outputs
and A1(Out, A, B);
//Gate level description of 2 inputs and 1 output AND gate
endmodule
module stim; //Stimulus module
reg A,B; //Always make inputs as Reg or Registers
wire Out; //Always make outputs as wire
and_gate G1(Out, A, B); //Instantiation of main module (i.e. and_gate)
initial
begin
A=0;B=0;
#10
begin A=0;B=1;end
#10
begin A=1;B=0; end
#10
begin A=1;B=1; end
40
#10
begin A=1;B=1; end
end
endmodule
Input A
0
0
1
1
Truth Table For 2 Inputs AND Gate

Input B
Output Out
0
0
1
0
0
0
1
1
Timing Diagram Verification for the written code:
Some important things that we can see from the above code are:
The module always start with keyword module
Inside module () we define inputs and outputs but their sequence is not important
But in case of gate level description it is very imp that output must be written before the
inputs i.e. AND (Output, Input1, Input2 ...Input n)
We can also define additional wires i.e. Links other than input or output as explained in
the second example below
Some keywords for gate level description are:
and A1(output(s), input1, input2, input3..input n)
or
P1(output(s), input1, input2, input3..input n)
not
N1(output(s), input1, input2, input3..input n)
nand D1(output(s), input1, input2, input3..input n)
nor
H1(output(s), input1, input2, input3..input n)
xor
S1(output(s), input1, input2, input3..input n)
xnor Q1(output(s), input1, input2, input3..input n)
buf
B1(output(s), input1, input2, input3..input n)
Stimulus module is used to verify the results that the code is working in a right fashion
or not.
At the end draw the truth table for the AND gate and verify your code according the
output in the timing diagram and in the truth table

41
Dataflow Model Verilog Code:

module and_gate (Out, A, B); //Starting of module and defining inputs and outputs
input A, B;
//inputs
output Out;
//outputs
assign Out=A&B;
//Data flow description of 2 inputs and 1 output AND gate
endmodule
module stim; //Stimulus module
reg A,B; //Always make inputs as Reg or Registers
wire Out; //Always make outputs as wire
and_gate G1(Out, A, B); //Instantiation of main module (i.e. and_gate)
initial
begin
A=0;B=0;
#10
begin A=0;B=1;end
#10
begin A=1;B=0; end
#10
begin A=1;B=1; end
end
endmodule
The most important thing in data flow is the symbols that are used for different gates following
are the symbols that are usually used for different gate
Gate
AND
OR
NOT
XOR
Symbol Used
&
|
~
^
Hence from the above timing diagram we can see that both out codes perform the same task the
difference is of level of abstraction being used i.e. data flow or gate level
Verilog code for a bit complex circuit.
Used it as WIRE
in verilog code
A
B

42

module test(A,B,C,x,y);
input A,B,C;
output x,y;
wire W;
and
A1(w,A,B);
not
N1(y,C);
or
S1(x,w,y);
endmodule
module stim;
reg A,B,C;
wire x,y;
test TT(A,B,C,x,y);
initial
begin
A=0;B=0;C=0;
#10 begin A=0;B=0;C=1; end
end
endmodule
Truth Table
Input A
0
0
0
0
1
1
1
1
Truth Table for the given circuit

Input B
Input C
Output y
0
0
1
0
1
0
1
0
1
1
1
0
0
0
1
0
1
0
1
0
1
1
1
0
Output x
1
0
1
0
1
0
1
1

43
Timing Diagram Verification
Dataflow Model Verilog Code:

input A,B,C;
output x,y;
wire W=A&B;
assign y= ~ C;
assign x=W | y;
endmodule
module stim;
reg A,B,C;
wire x,y;
test TT(A,B,C,x,y);
initial
begin
A=0;B=0;C=0;
end
endmodule

44
Lab Report Questions:

Q1: Write some properties of all four levels of abstraction described above (Hint: use internet
for help)?
Q2: Find all the keywords used in Verilog (Hint: use internet for help)?
Q3: What is the difference between NET and REG in Verilog?
Q4: Write Verilog code for the following code and also attach the timing diagrams and the truth
table (Hint: Take help from your teacher)?
A
B
X
Q5: Write Verilog code for the following code and also attach the timing diagrams and the truth
table (Hint: Take help from your teacher)?
A
OUT

45
Exp No. 15
UNDERSTATING BEHAVIORAL MODELING AND LEXICAL

CONVENTIONS OF VERILOG HDL
Objectives:
E. Understand the design methodologies.
F. Lexical conventions.
G. Data types being used in Verilog
H. Develop code in Verilog using behavioral model
I. Have some concept of gate delays
J. Submit the lab report along with the answers of given questions.
PreLab:
Design Methodologies:
There are two basic types of design methodologies: a top-down design methodology and a
bottom-up design methodology. In a top down methodology, we define the top level block and
identify the sub blocks necessary to build the top level block. We further subdivide the sub
blocks until we come to leaf cells, which are the cells that cannot be further subdivided. The
following figure shows the top-down design
Top Level Block
Sub-Block 1
Leaf Cell
Sub-Block 2
Leaf Cell
Sub-Block 3
Leaf Cell
Leaf Cell
Figure: Top down design methodology

In a bottom up design methodology, we first identify the building blocks that are available to
us. We build bigger cells, using these building blocks. These cells are then used for higher-level
46
blocks until we build the top level block in the design. Following figure shows the bottom-up
design process
Top Level Block
macro cell 1
macro cell 1
Leaf Cell
Leaf Cell
macro cell 1
Leaf Cell
Leaf Cell
Figure: Bottom-up design methodology

Lexical Conventions in Verilog
White Spaces:
Blank space (\b), tabs (\t), and new lines (\n) comprise the white spaces. White space is
ignored by the Verilog except when it separates tokens. White space is not ignored in strings
Comments:
Comments can be inserted into the code for readability and documentation. There are two
ways to write comments. A one line comment starts with //. Verilog skips from that
position to the end of the line. A multiple comment starts with /* and ends with */.
a = b && c; //This is a one line comment

/* This is a multiple line
Comment*/
/* This is /* an illegal */ comment */
/* This is // a legal comment */
Operators:

47
Operators are of three types: unary, binary and ternary. Unary operators precede the
operands. Binary operators appear between two operands. Ternary operators have two
separate operators that separate three operands
a = ~ b; // ~ is a unary operator
a = b && c; // && is a binary operator
a = b? c : d; // ?: is a ternary operator
Number Specification:
Sized Numbers
Sizes numbers are represented as <size><base format><number>.
<size> is written only in decimal and specifies the number of bits in the number.
Legal base formats are decimal (d or D), hexadecimal (h or H), binary (b or B) and
octal (o or O). the number is specifies as consecutive digits from
0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f. only a subset of these digits is legal for a particular
base.
4b1111
12habc
16d255
//This is a 4-bit binary number

//This is a 12-bit hexadecimal number
//This is a 16-bit decimal number
Unsized Numbers
Numbers that are specifies without a <base format> specification are decimal
numbers by default. Number that are written without <size> specification have a
default no of bits that is simulator or machine specific (must be at least 32)
23456
hc3
o21
//This is 32-bit decimal number by default

//This is a 32-bit hexadecimal number
//This is a 32-bit octal number
X or Z values
Verilog has two symbols for unknown and high impedance values. These values are
very important for modeling real circuits. An unknown value is denoted by an x. A
high impedance value is denoted by z.
12h13x
//This is a 32-bit hex number 4 least significant bits unknown

48
6hx
32bz
//This is a 16-bit hex number

//This is a 32-bit high impedance number
Strings:
A string is a sequence of characters that are enclosed by double quotes. The restriction on a
string is that is must contain on a single line, that is without carriage return. it cannot be on
multiple lines
Hello Verilog World

a / b
//is a string
//is a string

49
Gate Delays in Verilog

In Verilog the date delays is generally represented by # symbol along with the gate function
Post Lab:
Answer all questions in this lab and submit then in your lab report.
Lab Work:
Simple circuit with delays
A
B
30ns
20ns
Y
10ns
Verilog Code:
input A,B,C;
output x,y;
wire W;
and #30
not #10
or #20
endmodule
Gate Delay of 10n Seconds
A1(w,A,B);
N1(y,C);
S1(x,w,y);
module stim;
reg A,B,C;
wire x,y;
test TT(A,B,C,x,y);
initial
begin
A=0;B=0;C=0;
50

#100 $finish;
end
endmodule
Verilog code for half adder.

Y
Sum
Carray
module test(x,y,Sum,Carry);
input x,y;
output Sum,Carry;
xor
A1(Sum,x,y);
and
N1(Carry,x,y);
endmodule
module stim;
reg x,y;
wire Sum,Carry;
51
test TT(x,y,Sum,Carry);
initial
begin
x=0;y=0;
#10 begin x=0;y=1; end
#10 $finish;
end
endmodule
Timing Diagram Verification

Q1: Write all System tasks and compiler directives along with their functions performed like
$<keyword> $display, $monitor, $time, $stop, $finish etc
(Hint: use internet for help)?
Q2: Explain the syntax and usage of Integer, Real, Time Register data types used in Verilog.
Also explain the syntax and usage of Arrays and Vectors (Hint: use internet for help)?
Q3: Write the difference between INITIAL block and ALWAYS block used in Verilog and also
explain the difference between TASKS and FUNCTIONS used in Verilog?
Q4: Explain the usage of FOLK and JOIN statements in Verilog with the help of example?
Q5: Write Verilog code (in behavior model) for the following diagram and also attach the
timing diagram and the truth table (Hint: Take help from your teacher)?

52
Full Adder
X
Y
Sum
Carray
Q6: Write Verilog code (in behavior model) for the following diagram and also attach the
timing diagram and the truth table (Hint: Take help from your teacher)?
4-Bit Full Adder

B[3]
A[3]
FA3
B[2]
C3
B[1]
A[2]
FA2
C2
A[1]
FA1
B[0]
C1
A[0]
FA0
Cin
Cout
S[3]
S[2]
S[1]
S[0]

53
Exp No. 16
WRITING MORE CODES IN VERILOG HDL AND

UNDERSTANDING THE GATE DELAYS
Objectives:
K. Understand some of the Verilog basic concepts.
L. Understand the module structure in Verilog.
M. Understanding port connection rules used in Verilog.
N. Defining gate delay types.
O. Submit the lab report along with the answers of given questions.
Modules:
A module in Verilog consists of the following parts:
Module Name,
Port List, Port Declaration (if ports present)
Parameters (optional)
Declaration of wires,
regs and other variables
Data flow statements

(Assign)
Instantiation of lower
Level modules
Always and initial blocks.

All behavioral statements
Go in these blocks.
Tasks and Functions
endmodule statement
Components of a Verilog module
54
Port Connection Rules:

One can visualize a port as consisting of two units. One unit that is internal to the module and
another that is external to the module. The internal and external units are connected. There are
rules governing ports connections when modules are instantiated within other modules. The
Verilog simulator complains if any port connection rules are violated. These rules are simulated
in the following figure:
net
net
input
net
reg or net
inout
output
reg or net
net
Port Connection Rule

Inputs:
Internally, input ports must be of the type net. Externally, the inputs can be connected to a
variable which is a reg or a net.
Outputs:
Internally, output ports can be of type reg or net. Externally, outputs must always be
connected to a net. They cannot be connected to a reg.
Inouts:
Internally, inout ports must always be of type net. Externally inout ports must always be
connected to a net.
Width matching:
It is illegal to connect internal and external items of different items of different sizes when
making intermodule port connections. However, a warning is typically issued that the
widths do not match.
Unconnected Ports:
Verilog allows ports to remain unconnected. For example, certain ports might be simply for
debugging, and you might not be interested in connecting them to the external signals

55
Gate Delays in Verilog:

There are three types of delays in Verilog HDL i.e. Rise, Turn off and Fall delays
Rise delay:
The rise delay is associated with a gate output transition to a 1 from another value
1
0, x
or z
t_rise
Fall delay:
The fall delay is associated with a gate output transition to a 0 from another value
1, x
or z
t_fall
Turn-off delay:
The turn off delay is associated with a gate output transition to the high impedance value
(x) from another value.
If the value changes to x, the minimum of the three delays is considered
Post Lab:
Answer all questions in this lab and submit them in your lab report.

56
Lab Work:
Create the Verilog code of the following diagrams in the lab. (Using any model, but most
preferably BEHAVIOURAL MODEL)
1)
A
output
A>B
output
A<B
input
4-bit
Comparator
B
input
A==B
output
2)
S1
input
input
input
input
MUX
4X1
Selection
Selection
S2
output
OUT
3)
D
Q
CLK
D-LATCH
(not)

Q1: Explain the difference between continuous assignment and implicit continuous
assignment with the help of an example in data flow models?
57
Q2: Define at least 5 characteristics of continuous assignment?

Q3: What is the meaning of blocking assignment and non-blocking assignment, Explain
with example?
Q4: Define and explain all 4 types of Loops used in Verilog (i.e. While, For, Repeat and
Forever) by giving at least 2 examples of Verilog code for each?
Q5: Explain the characteristics of the following types of blocks used in Verilog?
Sequential Blocks
Parallel Blocks
Nested Blocks
Named Blocks
Q6: Write a Verilog code in behavioral model for 4-bit up counter?

Q7: Write a Verilog code in behavioral model for JK-Flip flop?

58

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Lab Manual, Digital Logic Design

FAMILIARIZATION WITH DIGITAL LOGIC TRAINER

Figure 1: NB-09 Digital Logic Trainer

Lab Manual, Digital Logic Design

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------Digital System Lab,CPED, UET Taxila

Lab Manual, Digital Logic Design

VERIFICATION OF TRUTH TABLE OF BASIC LOGIC

Truth Table of AND Gates

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------Digital System Lab,CPED, UET Taxila

Lab Manual, Digital Logic Design

Lab Manual, Digital Logic Design

Truth Table of NOT Gates.

Truth Table of NAND Gates

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------Digital System Lab,CPED, UET Taxila

Lab Manual, Digital Logic Design

Truth Table of NOR Gates

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------Digital System Lab,CPED, UET Taxila

Lab Manual, Digital Logic Design

IMPLEMENTATION OF MULTIVARIABLE BOOLEAN

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------Digital System Lab,CPED, UET Taxila

Lab Manual, Digital Logic Design

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------Digital System Lab,CPED, UET Taxila

Lab Manual, Digital Logic Design

VERIFICATION OF DEMORGANS THEOREM

F 2 = x '. y '. z '

F 4 = x '+ y '+ z '

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------Digital System Lab,CPED, UET Taxila

Lab Manual, Digital Logic Design

Now we shall check this logic circuit by the Truth Table.

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------Digital System Lab,CPED, UET Taxila

Lab Manual, Digital Logic Design

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------Digital System Lab,CPED, UET Taxila

Lab Manual, Digital Logic Design

TO REALIZE HALF & FULL ADDER USING BASIC LOGIC GATES.

Now we write Boolean function from above Truth Table as

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------Digital System Lab,CPED, UET Taxila

Lab Manual, Digital Logic Design

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------Digital System Lab,CPED, UET Taxila

Lab Manual, Digital Logic Design

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------Digital System Lab,CPED, UET Taxila

Lab Manual, Digital Logic Design

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------Digital System Lab,CPED, UET Taxila

Lab Manual, Digital Logic Design

Boolean functions for one bit Magnitude Comparator

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------Digital System Lab,CPED, UET Taxila

Lab Manual, Digital Logic Design

USING XOR GATES AND BASIC LOGIC GATES

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Lab Manual, Digital Logic Design

Now we simplify outputs of 2 Bit Magnitude Comparator by k-map technique.

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------Digital System Lab,CPED, UET Taxila

Lab Manual, Digital Logic Design

k-maps for outputs of 2 Bit Magnitude Comparator.

Lab Manual, Digital Logic Design

L = A '1 B 1 + A '0 B 0 ( A 1 + B 1 ) '

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------Digital System Lab,CPED, UET Taxila

Lab Manual, Digital Logic Design

G = A 1 B '1 + A 0 B '0 ( A 1 + B 1 ) '

L = A '1 B 1 + A '0 B 0 ( A 1 + B 1 ) '

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Lab Manual, Digital Logic Design

DESIGN & IMPLEMENTATION OF A 2 x 4 DECODER

data input lines