Lecture 12

Integrated circuits
Basic fabrication steps
IC devices

Integrated Circuits

First hybrid IC: 5 devices

First monolithic IC: 6 devices

Invention:
1959 hybrid IC (Kilby)
1959 monolithic IC (Noyce)
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Technological Development: Trend

Moores law: 2 times increase in

components count every 18
month

Why Integrated Circuits

Technological reasons:
Higher performance
faster
higher density
more functionality
low power consumption,
Economical reasons:
More reliable
Cheaper
Classifications:
In terms of performance
linear (amplifiers, analog devices, )
digital (logic, memory)
In terms of design
monolithic
hybrid

Fabrication: Basic Steps

Fabrication: Basic Steps

Size comparison of a wafer to individual components.

(a) Semiconductor wafer. (b) Chip. (c) MOSFET and bipolar transistor.
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Fabrication: Lithography
Light absorbing layer
(iron oxide)

Quartz plate

Pattern for an entire wafer mask

Pattern for a single chip (die) - reticle
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Fabrication: Lithography

Minimum size of devices

resolution of lithography
UV (0.25 m) X-Ray (1 )
e-beam (10 KeV - 0.1)

Schematic diagram of an optical stepper.

Passive Components
IC Resistor
Conductance of a
square resistor
pattern

G = q p

Wx j

L
1
L
R = R
G W

Na = g

W
L

Sheet resistance

Passive Components
IC Capacitor
Capacitor per unit area:

C=

i
d

( F / cm 2 )

To increase C high
i Si3N4 and Ta2O5

High doping to decrease series resistance

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Charge-coupled device (CCD): Idea

MOS capacitor:
Positive bias pulse potential
well for electrons
t < thermal relaxation time
empty well
Can be used for temporary
storage of chage
Dinamic injection, movement and
collection of charges CCD
(Boyle and Smith, Bell, 1969)

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Charge-coupled device (CCD): Basic structure

Applications:
Signal
processing
Imaging

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MOSFET Technology

Perspective view of an
n-channel MOSFET.

Reduction in the area of the

MOSFET as the gate length
(minimum feature length) is
reduced.
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MOSFET Technology (NMOS)

Formation of SiO2, Si3N4, and photoresist layer.

(define device area)

(Source and drain)

P-doped
oxide
deposition

(threshold adjustment)

Gate

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Complementary MOS (CMOS)

MOS Inventor:
Vin=0
p-channel MOSFET on (VGS=-VDD)
n-channel MOSFET off (VGS=0)
Vout=VDD

One MOS is always off No

(low) current flow Low
power consumption

Applications:
- logic
- memory

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Memory Devices

Memory: store digital information in terms of bits (binary digits)

Types:
Volatile
- Static Random Access Memory (SRAM)
- Dynamic Random Access Memory (DRAM)
Non-volatile
Flash Memory

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Random Access Memory (RAM)

(Random access fast

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Static Random Access Memory (SRAM)

Memory cell:
2 cross-coupled CMOS + 2 access
MOS
Bit: state of the flip-flop (i.e outputs
of the inventors)

Wordline n

Complementary

Read Both bitlines are charged to the same V

Write One of the bitlines is grounded

Advantage: Static memory

Disadvantage: Large space
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Dynamic Random Access Memory (DRAM)

Information: charge on an MOS
capacitor (empty or charged)
0 filled with charge
1 - empty

Advantage: Compact
Disadvantage: Requires dynamic
refreshment (due to leakage of
the capacitor)

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Flash Memory

Flash memory: MOSFET

with an extra gate (floating
gate)

Information - threshold voltage

of a MOSFET:
0 low VT
1 high VT

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Flash Memory
Programming:

Erasing:

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Flash Memory

Advantages:
Non-volatile
Compact
Disadvantage: Slow (ms)
Applications:
Mobile phones
Cameras
USB

Growth curves for different

technology drivers.
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