ECE 0142 Computer Organization

Spring 2015
Homework #5
Due: before or in-class February 10
From the textbook do the following:
Exercises:
4.1.1(parts a and b); 4.1.2 (parts a and b); 4.1.3 (parts a and b)
4.1.4a; 4.1.5a; 4.1.6a
4.2.1b; 4.2.2b; 4.2.3b
4.6a (do part a for all questions associated with exercise 4.6, i.e. 4.6.1 through 4.6.6)

Supplemental Problems
The purpose of The following problems is to practice analysis and design processor datapath
architectures. Steps toward designing a processor:
i. Analyze the instruction set architecture (ISA) and understand the datapath requirements.
ii. Select a set of datapath components (i.e. registers, multiplexers, ALUs, ect.) and establish
a clocking methodology.
iii. Construct a datapath to meet the ISA requirements.
iv. Analyze how to implement each instruction and determine the setting of the various
control signals.
v. Design the controller.

1. Design data path logic that will allow any two of the following register transfers that do not
have the same destination to be done in one step.
AB:
AC:
CB:
BC:

2. A system is to have the following set of register transfers implemented using busses:
1 0 1
2 3 1 , 1 4 , 4 0
3 2 3 , 0 2
4 2 4 , 4 2
a) For each destination register, list all of the source registers.
b) For each source register, list all of the destination registers.

c) Assume that each register will have a single bus as its input. Using the minimum number
of buses, draw a block diagram of the system showing the registers and buses and the
connections between them.
3. For the datapath architecture shown below, specify the fewest microoperations and the
corresponding control signals to compute [2] 2[1] + 3.

The ALU functions are

Func
0
1
2
3

Operation
nop
add
sub
nor

RTL

+

( )