Bi 1

A,

B,

T s ghp ni xc nh tn IC nh. Xc nh di a ch cn ghp ni (lm bc 1 v bc 2). Lu

: Chn CE = Chip Enable CS = Chip Select.
Bi 2

A,

B,

a. Vit chng trnh iu khin LED 7 thanh sng s 9 khi kha K ng v s 0 khi K m.
b. Gii m a ch cng v lp trnh cho 8255 hot ng ch 0. Thc hin khi to LCD bng
chng trnh con LCD_Init. Sau nu chn PC5 pht tn hiu cho R/~W ghi d liu th LCD
c ghi Hello TC406 bng chng trnh con LCD_Write.
Bi 3
Cho 8255 c a ch cng c s l 100H, s dng chn A2 A1 ca VXL 8086 vi chn A1 A0 ca
8255. Cng A c ni vi 1 Cng tc SW v c ni u cn li ca SW ln ngun. C 8 LED n
c mc vo PB0->PB3 v PC4->PC7. Lp trnh iu khin 8 LED 8 LED sng ln lt vi hm
tr 1s c thit lp trc: DELAY_1S
Bi 4
Lp trnh bit PC4 ca 8255 VD trn ra 256 xung vi T = 50ms. rng xung l 50%.Gi thit
c sn chng trnh con TRE_25MS. Bit a ch cng C l 7CH.
Bi 5

Cho mch 8255 vi a ch c s l 30H, c kt ni vi cc

phn t ngoi vi n gin
nh trn hnh v. Vit chng trnh khi c V1>V2 th c trng
thi ca cng tc SW. Nu SW gt sang GND th LED tt.
SW m th LED sng. Gi thit KTT thc hin chc nng
so snh vi V1>V2 th Vout = 1 v
ngc li.

Bi 6
K56
A3-A2(8086)A1-A0(8255)
A4-A6-A0(8086)A-B-C(138)
A1-A5-A7(8086)G1-G2A-G2B(138)
Y3(138) CS(8255)
PA0-PA2-PA4-PA6(8255) A-B-C-D(7447)
8 chn ra ca 7447 ni vo LED 7 thanh
Lp bng gii m 7SEG v vit chng trnh mi ln bm SW th 7SEG gim i 1. Gi thit ban u
7SEG hin th s 9.
Bi 7
Ghp ni 8088 vi b nh, s dng b gii m 74LS138 hoc 74LS139:
a 192 KB b nh SRAM s dng SRAM 62256, bt u t a ch 30000H.
b B nh EPROM c di a ch 80000H-9FFFFH s dng EPROM 2732
Bi 8
Ghp ni 8086 ng thi vi 64K EPROM 27128 v 128K SRAM 62256. Bit rng a ch u ca
SRAM l 00000H v a ch cui ca EPROM l FFFFFH.