Dynamic Combinational

Circuits
Dynamic circuits
Charge sharing, charge redistribution

Domino logic
np-CMOS (zipper CMOS)

James Morizio

Dynamic Logic
Dynamic gates use a clocked pMOS pullup
Two modes: precharge and evaluate
A

2
1

2/3

Static

4/3

Pseudo-nMOS

Precharge

Dynamic
Evaluate

Precharge

Y
James Morizio

The Foot
What if pulldown network is ON during
precharge?
Use series evaluation transistor to prevent fight.

precharge transistor
Y

inputs

Y
f

inputs

Y
f

foot
footed

James Morizio

unfooted

Dynamic Logic
VDD

Mp

VDD

Out
CL

In1
In2
In3

PDN

In1
In2
In3

Me
n network

2 phase operation:

Me

PUN
Out

Precharge

Mp

CL

p network

Evaluation
James Morizio

Logical Effort
Inverter

unfooted

footed

2
2

NAND2

Y
gd
pd

= 1/3
= 2/3

Y
gd
pd

= 2/3
= 3/3

3
3

NOR2
Y

gd
pd

= 2/3
= 3/3

gd
pd

James Morizio

= 3/3
= 4/3

1
2

B
2

Y
gd
pd

= 1/3
= 3/3

Y
gd
pd

= 2/3
= 5/3

Dynamic Logic
N+2 transistors for N-input function
Better than 2N transistors for complementary static CMOS
Comparable to N+1 for ratio-ed logic

No static power dissipation

Better than ratio-ed logic

Careful design, clock signal needed

James Morizio

Dynamic Logic: Principles

VDD

Mp

Precharge
Out
CL

In1
In2
In3

PDN

Me

= 0, Out is precharged to VDD by Mp.

Me is turned off, no dc current flows
(regardless of input values)

Evaluation
= 1, Me is turned on, Mp is turned off.
Output is pulled down to zero depending
on the values on the inputs. If not,
precharged value remains on CL.

Important: Once Out is discharged, it cannot be charged again!

Gate input can make only one transition during evaluation
Minimum clock frequency must be maintained
Can Me be eliminated?
James Morizio

Example
VDD
Mp

Out

Ratio le s s
No Static Po we r Cons umptio n

A
C
B

Nois e Marg ins s mall (NML)

Requires Cloc k

Me

James Morizio

Dynamic 4 Input NAND Gate

James Morizio

Cascading Dynamic Gates

VDD
Mp

VDD

Mp
Out2

Out1

In
Out1

In

VTn

Out2

Me

Me

Internal nodes can only make 0-1 transitions during evaluation period
James Morizio

10

Monotonicity
Dynamic gates require monotonically rising inputs
during evaluation

0 -> 0
0 -> 1
1 -> 1
But not 1 -> 0

violates monotonicity
during evaluation
A

Precharge

Evaluate

Precharge

Y
Output should rise but does not

James Morizio

11

Monotonicity Woes
But dynamic gates produce monotonically falling
outputs during evaluation
Illegal for one dynamic gate to drive another!
A=1

Precharge

Evaluate

Precharge

X
X monotonically falls during evaluation
Y
Y should rise but cannot

James Morizio

12

Reliability Problems Charge Leakage

VDD

Mp
Out
(1)

CL

t
Vout

(2)

precharge

evaluate

A=0

Me

(a) Leakage sources

(b) Effect on waveforms

(1) Leakage through reverse-biased diode of the diffusion area

(2) Subthreshold current from drain to source
Minimum Clock Frequenc y: > 1 MHz
James Morizio

13

Leakage
Dynamic node floats high during evaluation
Transistors are leaky (IOFF 0)
Dynamic value will leak away over time
Formerly miliseconds, now nanoseconds!

Use keeper to hold dynamic node

Must be weak enough not to fight evaluation
weak keeper

1 k
2

James Morizio

14

Charge Sharing (redistribution)

VDD

Assume: during precharge, A and B are 0, Ca is discharged

During evaluation, B remains 0 and A rises to 1
Charge stored on CL is now redistributed over CL and Ca

Mp
Out

CL

Ma
X

B=0

Mb

Me

Ca
Cb

CLVDD = CL Vout(t) + CaVX

VX = VDD - Vt, therefore
Vout(t) = Vout(t) - VDD =

Ca
(VDD-Vt)
CL

Desirable to keep the voltage drop below threshold

of pMOS transistor (why?) Ca/CL < 0.2
James Morizio

15

Charge Sharing
Dynamic gates suffer from charge sharing

A
B=0

Y
CY

x
Cx

A
Y
Charge sharing noise
x

CY
Vx = VY =
VDD
C x + CY
James Morizio

16

Charge Redistribution - Solutions

VDD

VDD
Mp

Mbl

Mp

Out

Out
A

Ma

Ma

Mb

Mb

Me

(a) Static bleeder

Mbl

Me

(b) Precharge of internal nodes

James Morizio

17

Secondary Precharge
Solution: add secondary precharge transistors
Typically need to precharge every other node

Big load capacitance CY helps as well

Y
A

secondary
precharge
transistor

James Morizio

18

Domino Logic
VDD

Mp

VDD

Out1

Mp

VDD
Mr
Out2

In1
In2
In3

PDN

Me

PDN

In4

Static Inverter
with Level Restorer

Me

Static inverters
between dynamic stages

James Morizio

19

Domino Gates
Follow dynamic stage with inverting static gate
Dynamic / static pair is called domino gate
Produces monotonic outputs

domino AND
W

Precharge

Evaluate

Precharge

A
B

Y
Z

dynamic static
NAND inverter

A
B

James Morizio

X
C

A
B

20

Domino Logic - Characteristics

Only non-inverting logic
Very fast - Only 1->0 transitions at input of inverter
Precharging makes pull-up very fast
Adding level restorer reduces leakage and
charge redistribution problems
Optimize inverter for fan-out
James Morizio

21

Domino Optimizations
Each domino gate triggers next one, like a string of
dominos toppling over
Gates evaluate sequentially but precharge in parallel
Thus evaluation is more critical than precharge
HI-skewed static stages can perform logic

S0

S1

S2

S3

D0

D1

D2

D3
H

S4

S5

S6

S7

D4

D5

D6

D7

James Morizio

22

Dual-Rail Domino
Domino only performs noninverting functions:
AND, OR but not NAND, NOR, or XOR

Dual-rail domino solves this problem

Takes true and complementary inputs
Produces true and complementary outputs
sig_h

sig_l

Meaning

Precharged

invalid

Y_l

Y_h

inputs

James Morizio

23

Example: AND/NAND
Given A_h, A_l, B_h, B_l
Compute Y_h = A * B, Y_l = ~(A * B)
Pulldown networks are conduction complements
Y_l

= A*B
A_l

B_l

A_h

Y_h
= A*B

B_h

James Morizio

24

Example: XOR/XNOR
Sometimes possible to share transistors
Y_l
= A xnor B

A_h

A_l
B_l

Y_h
A_l

A_h

= A xor B

B_h

James Morizio

25

Domino Summary
Domino logic is attractive for high-speed circuits
1.5 2x faster than static CMOS
But many challenges:
Monotonicity
Leakage
Charge sharing
Noise

Widely used in high-performance microprocessors

James Morizio

26

np-CMOS (Zipper CMOS)

VDD
Mp

In1
In2
In3

PDN

VDD

Out1

Me

PUN

In4

Out2

Me

Mp

Only 1-0 transitions allowed at inputs of PUN

Used a lot in the Alpha design
James Morizio

27

np CMOS Adder
VDD

A1

VD D

VDD

B1

B1

A1

A1

B1

A0
B0

B0

Ci1

A0

B0

Ci0

A1
B1

Ci1

VDD

S1

Ci1

VDD

A0

Ci2

VD D

Ci0

VDD

B0
A0
Ci0

S0

Carry Path

James Morizio

28

CMOS Circuit Styles - Summary

James Morizio

29