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-1
-2 -
-
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-2
-:
(1 ) (Boolean Arithmetic )Boolean
(Arithmetic ) (And,Or,Not
.
)(Bit Half Adder 2
)Sum = (x AND NOT y) OR (NOT x AND y
)Carry =(x AND y
(2
) (Flip Flop )(Register
( ) ( :
(1 )(Synchronous
)(Clocked
(2 ):(Asynchronous
)(Non-Clocked
(
(1
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(2
) (PLD ) (ROM ) (PAL )
(PLAs
) (PLD
) ( PLD
)(PAL
) : (1 )(PAL
( )(ASIC
-:
(1
(2
( )(CPLD
) (PLD
) (PLD ) (PAL
)) CPLD
( )Field Programmable Gate Arrays (FPGA
) (CPLD
) (FPGA
) (Flip-Flop
)(CPLD
) : (2 )(FPGA
4
-
)FPGA
( ) (FPGA
) (LOGIC CELLS
)(Flip-Flop )
(Vendor )(Family )(FPGA
FPGA
)(Logic Block)(Logic Element
( )(Logic Cells )LUT (Look up Tables )
(ROMs FPGA SRAM)Dual
(Port Memory) (CAM )(HDL
schematic entry
( ) (Routing Resources )(FPGA
)(FPGA
Memory, LUT & Logic Cells
( pins
)(PINs
)(FPGA
)(TTL) (CMOS) (PCI ) (AGP . )
(FPGA
( pins ) (Clock )(PLL ) (FPGA
) (Clock ) (Reset ) (FPGA
) (Clock ) (PLL ) (ClockMultiplier )(Divider
-6 )(FPGA
) (FPGA
.1 ) (Demo
.2 ) ( Applications
-:
)
) (FPGA
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(External Headers
) (Interface Chips
.2
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.1 ) (FPGA
)(FPGA
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- 12
- 13
) (FPGA
) (FPGA
) (FPGA
) (FPGA
) (FPGA )(FPGA
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- 14
) (FPGA )
(FPGA ) (HDL ) (HDL
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-
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(1 ) ( ) (schematic Entry
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(2 ) (HDL
) (HDL VHDL & Verilog
..VHDL
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- )(Synthesis
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schematic Entry
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FPGA
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) (Hardware Design
) HDL )
( AND,OR,NOT
)
( Loops,Case,If )(
) ( HDL ) (Verilog )
(VHDL )(AHDL
CPLD
)LSI (Large Scale Integration
CPLD) (Complex Programmable Logic Device )
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CPLD FPGA
IC .
: 7400
NAND 7404 NOT
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CPLD
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XC9500 XILINIX
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XC9500
: PLCC Plastic Leaded Chip Carrier
:FB Function Block 2FB
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:Gates .
:Macrocells full
adder .registers
:Pin .
CPLD
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10000.
.
XC9500 .
: XC9572 1600 84 $
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:FPGA
FPGA
:FPGA
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frame
. ASIC FPGA
.
-2 :
FPGA
.
.
:FPGA
FPGA soft ware
hard ware
(
.
NAND FILP_FLOP
AND
FPGA
AND AND
IC 4066
VHDL
Very high speed integrated circuits Hardware Description Language
) ( )
( ) application-specific integrated circuits ( ASIC
.
graphics VGA
.
VHDL
) (
Header-1
Interface (Entity)-2
Functions(Architecture)-3
Header
:
;LIBRARY library_name
;USE library_name.package_name.ALL
:
;LIBRARY ieee
;USE ieee.std_logic_1164.ALL
IEEE std_logic_1164
.
.
Interface (Entity) :
:
ENTITY entity_name IS
PORT (in1,in2, :attribute data_type ;out1,out2,.:attribute da
;)ta_type
; END entity_name
,
,In1,in2
Attribute ..
VHDL
IN OUT INOUT
BUFFER )(
:Data_type
VHDL!!
std_logic-1 ) ( (on-off) 1-0
:std_logic_vector-2 ) (bus
(on-off) 1-0
:integer-3 )(bus
. bit std_logic
:
ENTITY my_first IS
; PORT ( x1,x2,x3 : IN STD_LOGIC
;)y: OUT STD_LOGIC_VECTOR (1 TO 5
;)c:BUFFER INTEGER RANGE 0 TO 4
; END my_first
y ( -and-or-not) x1,x2,x3
( y1,y2,y3,y4,y5) 5 1
) 3 4 C
(100= 4
.
:
VHDL
.
-- Operand 1
-- Operand 2
-- Output carry
-- Result
END Adder_ent;
ARCHITECTURE behavior OF Adder_ent IS
BEGIN -- behavior
Result <= (Op1 AND NOT Op2) OR (NOT Op1 AND Op2);
Carry <= Op1 AND Op2;
END behavior;
8 bit Adder
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY Adder_ent IS
PORT (
clk : IN std_logic;
-- System clock
rst_n : IN std_logic;
-- System reset
Op1 : IN std_logic_vector(7 DOWNTO 0); -- Operand 1
op2 : IN std_logic_vector(7 DOWNTO 0); -- Operand 2
Result : OUT std_logic_vector(7 DOWNTO 0)); -- Result
END Adder_ent;
ARCHITECTURE behavior OF Adder_ent IS
BEGIN -- behavior
PROCESS (clk, rst_n)
BEGIN -- PROCESS
Counter
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY Adder_ent IS
PORT (
clk : IN std_logic;
-- System clock
rst_n : IN std_logic;
-- System reset
Count : OUT std_logic_vector(7 DOWNTO 0)); -- Count
END Adder_ent;
ARCHITECTURE behavior OF Adder_ent IS
SIGNAL counter : std_logic_vector(7 DOWNTO 0); -- internal counter
BEGIN -- behavior
PROCESS (clk, rst_n)
BEGIN -- PROCESS
IF rst_n = '0' THEN
-- asynchronous reset (active low)
Counter <= (OTHERS => '0');
ELSIF clk'event AND clk = '1' THEN -- rising clock edge
Counter <= counter + 1;
END IF;
END PROCESS;
count <= counter;
END behavior;
7-Segment decoder
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Decoder IS
PORT (
InBin : IN std_logic_vector (3 DOWNTO 0);
Display : OUT std_logic_vector (6 DOWNTO 0));
END Decoder;
ARCHITECTURE rtl OF decoder IS
SIGNAL t : std_logic_vector (6 DOWNTO 0);
BEGIN
seg_process : PROCESS (InBin)
BEGIN
CASE InBin IS
WHEN "0000" => t <= "1111110";
WHEN "0001" => t <= "0110000";