Design of Analog CMOS Circuits

Using Gm/IDBased Methods

EEE 523 - Advanced Analog Integrated Circuits
Erik Mentze
01.27.12

References
1. F. Silveria et al. A gm/Id based methodology for the design of CMOS
analog circuits and its application to the synthesis of a silicon-on-insulator
micropower OTA, IEEE Journal of Solid-State Circuits, Sep. 1996, pp 13141319.
2. D. Foty, M. Bucher, D. Binkley, Re-interpreting the MOS transistor via the
inversion coefficient and the continuum of gms/Id, Proc. Int. Conf. on
Electronics, Circuits and Systems, pp. 1179-1182, Sep 2002.
3. B.E. Boser, Analog Circuit Design with Submicron Transistors, IEEE SSCS
Meeting, Santa Clara Valley, May 19, 2005, http://
www.ewh.ieee.org/r6/scv/ssc/May1905.pdf.
4. H.D. Dammak, et al. Design of Folded Cascoe OTA in Different Regions of
Operation through gm/ID Methodology, World Academy of Science,
Engineering, and Technology, 45, 2008.
5. P. Jespers, The gm/Id Methodology, a sizing tool for low-voltage analog
CMOS Circuits, Springer, 2010.
6. T. Konishi, et al, Design Optimization of High-Speed and Low-Power
Operational Transconductance Amplifier Using gm/ID Lookup Table
Methodology, IEICE Trans. Electron., Vol.E94-C, NO.3 March 2011.
7. B. Murmann, MOS Transistor Modeling Gm/ID-based Design, EE214
Course Reader, Stanford University, Stanford CA, 2011.

The Model Problem

Square Law
Nothing

Gm/ID

SPICE
EKV

Reality

Square Law Equations

Saturation
design term

operating point information

process constants

Triode
design term

process constant

operating point information

uCox (KP) Simulation

Dependence on: overdrive voltage, gate length, etc.

SPICE Model
Found One!

Process constants handled by curve fitting

BSIM 3v3 uses 110 parameters!

The Model Problem

Square Law
Nothing

gm/ID

SPICE
EKV

Reality

The purpose of any model: To give you the right answer!

Square Law Model:
Useful for hand calculations
Oversimplifies process constants
20%-80% Error

SPICE Model:
Useful for computer simulation
Curve Fitting for process constants
Excellent accuracy (if done properly)

Gm/ID Model:
Useful for hand calculations
<10% Error
Two approaches to process constants

Handling Process Constants

Analytical
Takes device physics into account, typically using the
EKV model
Derived expressions from physical device parameters

Experimental
Lookup table approach, storing device characteristics
generated by SPICE simulation or measurement results
The gm/ID lookup table methodology enables an
analytical design optimization by overwhelming the
inaccuracy observed in the square-law MOS transistor
model

gm/ID-Based Design
Set of normalized figures of merit to describe FET transistors
Transconductance Efficiency
FET Operating Point
Want large gm for as little current as possible

Current Density
How wide does the device need to be?

Transit Frequency
Want large gm, with as little Cgg as possible

Intrinsic Gain
Want large gm, with large ro (small go)

What is gm/ID?
A way of representing the FET operating point

Overdrive voltage () is only valid in strong inversion

can represent an equivalent bias condition for strong, moderate,
and weak inversion, with smooth transitions between each.
A design parameter that couples small signal transconductance
and large signal bias current.
How much bias current do I need to achieve a required amount
of transconductance?

A measure of efficiency to generate gm from a given ID

Large gm/ID value implies larger transconductance for a
constant current
Similar to normalized BJT transconductance:

Extracting Device
Characteristics
1. Vds set to Vpwr
2. Sweep Vgs: 0 to Vpwr
3. Measure required parameters:
- gm, Id, ro, Cgg

4. Repeat for various lengths

(fixed W)
Notes:
To a first order, the measurement is independent of Vds
Body effects are neglected
and thus measurements are independent of W

Weak Inversion
subthreshold

Moderate Inversion
Strong Inversion

Favors DC Gain

Favors BW

Strong Inversion

Weak Inversion

Strong Inversion

Weak Inversion

Lookup Table Functions

Can I avoid using a ruler on a printed out chart?
YES! By using a scripting language such as MATLAB,
Python, etc

Based on extracted data from SPICE simulations:

lookup.ft(fet, length, gm/id)
lookup.gmro(fet, length, gm/id)
lookup.idw(fet, length, gm/id)
lookup.gmid(fet, length, fom, fom_value)
lookup.length(fet, gmid, fom, fom_value)

Useful for:
Quick lookup while doing hand calculations
Design optimization scripts

Comparison to Square Law

Equations

Comparison to Square Law

Equations

Square law equations breakdown at Vov ~200mV

Comparison to Square Law

Equations

Good estimate of Vdsat: voltage required to extract gain

Gm/ID-Based Design
Replaces a set of equations to solve with a set of
figures of merit to balance
Complex process parameters are overwhelmed
with lookup charts (or lookup table functions)
Accurately models operation over weak,
moderate, and strong inversion
Avoids over-dependence on SPICE simulations

Sample Design Flow

1. From a given specification, determine the
required gm
2. Choose a bias current based on required gm and
desired gm/ID operating point.
3. Lookup transistor W from gm/ID vs. ID/W chart.
(L is typically chosen based on technology or gain
requirements)

Simple Example
Specs and Objectives:
tsmc18 process (3V)
RL=1k, CL=50fF, Ri=10k
DC Gain = -4 v/v
Estimate pole locations

Simple Design Flow

1. From the given specification, determine the
required gm
2. Choose a bias current based on required gm and
desired gm/ID operating point.
3. Lookup transistor W from gm/ID vs. ID/W chart.
(L is typically chosen based on technology and over gain
requirements)

Small Signal Model

Simple Design Flow

1. From the given specification, determine the
required gm
2. Choose a bias current based on required gm and
desired gm/ID operating point.
3. Lookup transistor W from gm/ID vs. ID/W chart.
(L is typically chosen based on technology and over gain
requirements)

Small Signal Model

Simple Design Flow

1. From the given specification, determine the
required gm
2. Choose a bias current based on required gm and
desired gm/ID operating point.
3. Lookup transistor W from gm/ID vs. ID/W chart.
(L is typically chosen based on technology and over gain
requirements)

Id/W=7.33

Simple Example

Test Circuit

Simulation Results
Parame
ter

Hand
Calc

Sim

%
error

Av(DC)

4.0 V/V

3.953
V/V

1%

gm

4 mS

4.089
mS

2.2%

gm/ID

10.0
S/A

10.15
S/A

1.5%

Simple Example Estimate

BW

Normalized Capacitance
Factors for approximating:

Simple Example Estimate

BW

ft = 7.01GHz

Simple Example Estimate

BW

Simulation Results

Summary of Normalized Design

Parameters
Primary Design
Parameters

Secondary Design
Parameters

Gm/ID-Based Design
Replaces a set of equations to solve with a set of
figures of merit to balance
Complex process parameters are overwhelmed
with lookup charts (or lookup table functions)
Accurately models operation over weak,
moderate, and strong inversion
Avoids over-dependence on SPICE simulations

OTA Simulation /
Optimization
1:K

M3

Vm

M31

M41

M1

M2

M4

Vp
CL

M51

1:K

M5

Design Choices:
K and gm set DC gain
K and gm set unity gain frequency
So which should I use? K or gm? Why not try both

gm/ID simulation results

Cload = 5pF
fun = 10MHz
AV(DC) = 1000 V/V

total current (mA)

tail current (mA)

gm/ID

Limitations
Lookup tables extracted from SPICE
simulations
Only as accurate as the SPICE curve fitting

Process and temperature corner cases

Body Effects
Cascode architecture

Drain-Source voltage variation

Appendix
Simple Current Mirror
Cascode Current Mirror

Current Mirror Design

Example
Design goals:
1. Good DC current matching
small gm/ID (strong inv)
2. Reasonable headroom

large gm/ID (weak inv)

3. High Output Resistance

small gm/ID (strong inv)

Design Option 1: gm/ID = 5

choose
lookup

Design Option 2: gm/ID =

10
choose
lookup

Cascode Current Mirror

Example

gmro
matching

Optimize separately
High gm/Id for gain
Low gm/Id for matching

Design Cascode Current

Source
choose
lookup
lookup