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Xilinx's Virtex Slice (3)

Altera's Apex Logic Element (4)

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IC 4066

VHDL
Very high speed integrated circuits Hardware Description Language
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Header-1
Interface (Entity)-2
Functions(Architecture)-3

 Header

:

;LIBRARY library_name
;USE library_name.package_name.ALL
:

;LIBRARY ieee
;USE ieee.std_logic_1164.ALL
IEEE std_logic_1164
.
.

Interface (Entity) :

:

ENTITY entity_name IS
PORT (in1,in2, :attribute data_type ;out1,out2,.:attribute da
;)ta_type
; END entity_name
,
,In1,in2
Attribute ..
VHDL
IN OUT INOUT
BUFFER )(
:Data_type
VHDL!!

std_logic-1 ) ( (on-off) 1-0
:std_logic_vector-2 ) (bus
(on-off) 1-0
:integer-3 )(bus
. bit std_logic
:

ENTITY my_first IS
; PORT ( x1,x2,x3 : IN STD_LOGIC
;)y: OUT STD_LOGIC_VECTOR (1 TO 5
;)c:BUFFER INTEGER RANGE 0 TO 4
; END my_first

 y ( -and-or-not) x1,x2,x3
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) 3 4 C
(100= 4
.
:
VHDL
.

Half adder (VHDL) - 10

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Adder_ent IS
PORT (
Op1 : IN std_logic;
op2 : IN std_logic;
carry : OUT std_logic;
Result : OUT std_logic);

-- Operand 1
-- Operand 2
-- Output carry
-- Result

END Adder_ent;
ARCHITECTURE behavior OF Adder_ent IS
BEGIN -- behavior
Result <= (Op1 AND NOT Op2) OR (NOT Op1 AND Op2);
Carry <= Op1 AND Op2;
END behavior;

8 bit Adder

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY Adder_ent IS
PORT (
clk : IN std_logic;
-- System clock
rst_n : IN std_logic;
-- System reset
Op1 : IN std_logic_vector(7 DOWNTO 0); -- Operand 1
op2 : IN std_logic_vector(7 DOWNTO 0); -- Operand 2
Result : OUT std_logic_vector(7 DOWNTO 0)); -- Result
END Adder_ent;
ARCHITECTURE behavior OF Adder_ent IS
BEGIN -- behavior
PROCESS (clk, rst_n)
BEGIN -- PROCESS

IF rst_n = '0' THEN

-- asynchronous reset (active low)
Result <= (OTHERS => '0');
ELSIF clk'event AND clk = '1' THEN -- rising clock edge
Result <= Op1 + op2;
END IF;
END PROCESS;
END behavior;

Counter

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY Adder_ent IS
PORT (
clk : IN std_logic;
-- System clock
rst_n : IN std_logic;
-- System reset
Count : OUT std_logic_vector(7 DOWNTO 0)); -- Count
END Adder_ent;
ARCHITECTURE behavior OF Adder_ent IS
SIGNAL counter : std_logic_vector(7 DOWNTO 0); -- internal counter
BEGIN -- behavior
PROCESS (clk, rst_n)
BEGIN -- PROCESS
IF rst_n = '0' THEN
-- asynchronous reset (active low)
Counter <= (OTHERS => '0');
ELSIF clk'event AND clk = '1' THEN -- rising clock edge
Counter <= counter + 1;
END IF;
END PROCESS;
count <= counter;
END behavior;

7-Segment decoder

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Decoder IS
PORT (
InBin : IN std_logic_vector (3 DOWNTO 0);
Display : OUT std_logic_vector (6 DOWNTO 0));
END Decoder;
ARCHITECTURE rtl OF decoder IS
SIGNAL t : std_logic_vector (6 DOWNTO 0);
BEGIN
seg_process : PROCESS (InBin)
BEGIN
CASE InBin IS
WHEN "0000" => t <= "1111110";
WHEN "0001" => t <= "0110000";

WHEN "0010" => t <= "1101101";

WHEN "0011" => t <= "1111001";
WHEN "0100" => t <= "0110011";
WHEN "0101" => t <= "1011011";
WHEN "0110" => t <= "0011111";
WHEN "0111" => t <= "1110000";
WHEN "1000" => t <= "1111111";
WHEN "1001" => t <= "1110011";
WHEN "1010" => t <= "1110111";
WHEN "1011" => t <= "0011111";
WHEN "1100" => t <= "1001110";
WHEN "1101" => t <= "0111101";
WHEN "1110" => t <= "1001111";
WHEN OTHERS => t <= "1000111";
END CASE;
Display
<= NOT t;
END PROCESS seg_process;
END rtl;