VHDL CODE

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--mux
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Mux entity
entity ent_mux is
port (
i0 : in std_logic;
i1 : in std_logic;
i2 : in std_logic;
i3 : in std_logic;
sel : in std_logic_vector(1 downto 0);
bitout : out std_logic
);
end ent_mux;
-- architecture Behavioral
architecture Behavioral of ent_mux is
begin
process(i0,i1,i2,i3,sel)
begin
case sel is
when "00" => bitout <= i0;
when "01" => bitout <= i1;
when "10" => bitout <= i2;
when "11" => bitout <= i3;
when others => bitout <= 'z';
end case;
end process;
end Behavioral;
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--Demux
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ent_demux is
port (
out0 : out std_logic;
--output bit
out1 : out std_logic;
--output bit
out2 : out std_logic;
--output bit
out3 : out std_logic;
--output bit
seld : in std_logic_vector(1 downto 0);
bitin : in std_logic
--input bit
);
end ent_demux;
architecture Behavioral of ent_demux is
begin
process(bitin,seld)
begin
case seld is
when "00" => out0 <= bitin; out1 <= '0'; out2 <= '0'; out3 <='0';
when "01" => out1 <= bitin; out0 <= '0'; out2 <= '0'; out3 <='0';
when "10" => out2 <= bitin; out0 <= '0'; out1 <= '0'; out3 <='0';
when "11" => out3 <= bitin;

out0 <= '0'; out1 <= '0'; out2 <='0';

when others => out3 <= 'x';

end case;
end process;

out0 <= 'x'; out1 <= 'x'; out2 <='x';

end Behavioral;
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MUX_DEMUX.vhdl
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========================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- entity md stand for mux demux
entity ent_mux_demux is
Port (
i0md : in std_logic;
i1md : in std_logic;
i2md : in std_logic;

i3md : in std_logic;
selmd : in std_logic_vector(1 downto 0);
out0md : out std_logic;
out1md : out std_logic;
out2md : out std_logic;
out3md : out std_logic;

)
end ent_mux_demux;
========================================
architecture arch_mux_demux of ent_mux_demux is
component ent_mux
port (
i0 : in std_logic;
i1 : in std_logic;
i2 : in std_logic;
i3 : in std_logic;
sel : in std_logic_vector(1 downto 0);
bitout : out std_logic;
)
end component;
component ent_demux
Port (
out0 : out std_logic;
out1 : out std_logic;
out2 : out std_logic;
out3 : out std_logic;
seld : in std_logic_vector(1 downto 0);
bitin : in std_logic --input bit
end component;

signal wire_mux : std_logic;

begin
mux: ent_mux
port map (

i0 =>

i0md,

i1 =>

i1md,

i2 =>

i2md,

i3 =>

i3md,

sel => selmd,

bitout => wire_mux
(;
demux: ent_demux
port map (
bitin => wire_mux,
seld=> selmd,
out0=> out0md,
out1=> out1md,
out2=> out2md,
out3=> out3md,

);
end arch_mux_demux;