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Questions and Answers PDF
Questions and Answers PDF
Ajit Pal
Professor
Department of Computer Science and Engineering
Gate Drain
substrate
Metal
Polysilicon
Oxide
Diffusion
Depletion
10
11
12
13
14
15
16
17
18
19
20
21
22
0/Vdd
0/Vdd
0
23
24
Idsn+Idsp
Vout=Vin - V
Reqn
RON
CL
Vdd
Id
Idsn
Idsp
Reqp || Reqn
| Vtp|
Vdd Vtn
Vout
Vdd - Vtn
| Vtp |
Vout
25
26
Vout
Vdd
Vdd
VOH
V
Vdd
2
Vdd
Vin
IN
=V
OUT
VOL
VIL V V
T IH
Vin
27
28
29
30
For
Ajit Pal, IIT Kharagpur
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32
Output Voltage
Input Voltage
33
Vdd
Vdd = Vtn +|
+|Vtp
Vtp|.
|. As the supply
voltage is reduced further,
Output Voltage
Vdd - IVtpI
Vtn
Vdd
Input Voltage
34
35
R AB =
L
t .W
L
A
ohm For L = W
RS =
= R ohm
36
Co =
A
D
Farads
37
Ln
Lp
td =
+
K nWn K pW p
CL
Vt
Vdd 1
Vdd
38
39
f =
2nt d
delay time.
40
41
42
Vdd
2/1
Vdd
Vin
2/1
Vout
1/2
V out
1/2
43
Vin
Q1
Vin
N1
t
Vout
N2
Q2
CL
CMOS
Vout
BiCMOS
N3
t
44
tmin
cL
= nf = e ln
cg
Ajit Pal, IIT Kharagpur
or ln y = n ln f
or n =
ln y
ln f
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47
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50
51
52
Vdd
Vdd
A
Cin
A
B
Cin
B
A
Co
B
A
Cin
Cin
A
Cin
B
B
A
Cin
Co
53
54
55
56
57
= CReq
58
59
D
1
f = a b + ab
Vdd
Vdd
V0
60
61
c
Ajit Pal, IIT Kharagpur
62
a
b
c
d
c
d
c
d
Step1
c
d
1
Ajit Pal, IIT Kharagpur
c
d
1
Step 2
63
a
b
c
d
1
Step 3
1
Step 4
64
Vdd
Pass
transistor
logic
O
Vdd
Pass
transistor
logic
Ans 2:
1
Vdd
a
F
c
a
0
b
0
d'
V dd
b
F
c
a
d'
c
1
Ajit Pal, IIT Kharagpur
A
B
S
FULL
ADDER
Cin
Co
67
Vdd
A
Realization using
Static CMOS is
given here.
It requires 28
transistors.
Cin
Cin
B
A
Co
B
A
Cin
Cin
A
Cin
B
B
A
Cin
Co
68
clk
requires 20 transistors.
clk
Cin
Cin
Co
B
B
Cin
S
S
B
clk
clk
Co
69
Cin
Cin
Cin
A A
A
0
A
B
Cin
A A
A
B
70
71
72
73
1
2
5 3
4 3
74
75
76
77
Clk
A
A
CL
1
B
1
C
0
C1
CL
S1
S
B C 2
C2
C1
C2
Clk=1
After the switches are closed, there will be redistribution of charges based
of charge conservation principle, and the voltage VA at node A is given by
VA, which is less than Vdd.
C LVdd = (C L + C1 + C 2 )V A.
Ajit Pal, IIT Kharagpur
CL
VA =
Vdd
(C L + C1 + C 2 )
78
79
Vdd
Clk
N-block
Clk
To next
stage
80
clk
clk
nblock
clk
clk
pblock
clk
clk
nblock
82
Combinational logic
to compute outputs
and next states
PI
PS
PO
NS
Latches
CLK
Combinational logic
to compute outputs
PS
PO
Combinational logic to
compute next states
NS
PI
Latches
CLK
83
0/0
s1
0/0
0/0
1/0
s3
s2
s4
1/0
1/0
1/1
0/0
Ajit Pal, IIT Kharagpur
84
PS
S1
S2
S3
S4
y2y1
00
01
10
11
x =0
00,0
10,0
11,0
00,0
0/0
s1
0/0
0/0
1/0
s3
s2
s4
1/0
1/0
1/1
0/0
Y2Y1, z
X=1
01,0
01,0
01,0
01,1
Ajit Pal, IIT Kharagpur
85
y1
y2
Y2
Y2 = x(y2y1 + y2y1)
Y1 = x + xy2y1
z = xy2y1
Y1
QD
QD
CLK
86
PI
ROM
Y3
y3
Y2
y2
Y1
y1
PS
NS
QD
QD
QD
DECODER
CLK
ENCODER
y3
y2
y1
x
z Y1Y2 Y3
Ajit Pal, IIT Kharagpur
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88
89
Vdd
Bit line C
T3
T4
T5
T6
T2
T1
Vss
Row select
Word line
Cross-coupled
sense amplifier
write circuitry
CLK
WB
Vss
WB'
Column
select
90
92
93
A=1
B=1
C=0
C1
CL
C2
94
C L V dd
=
C1 + C 2 + C 3
V new
V = V dd
CL
.V dd
C1 + C 2 + C L
C1 + C 2
.Vdd
C1 + C 2 + C L
C L .(C1 + C 2 ) 2
P = C L .Vdd .V =
Vdd
(C1 + C 2 + C L )
Ajit Pal, IIT Kharagpur
95
96
97
98
I1= ReverseReverse-bias p
p--n junction diode leakage current
I2 = Band
Band--toto-band tunneling current
I6 = Channel punchpunch-through
99
Active Power
Power (W)
0
10
-1
10
-2
10
Stand by Power
-3
10
-4
10
-5
10
-6
10
1.0
0.8
0.6
0.5
0.35
0.25
0.18
101
102
103
1.0
Normalized Delay
Normalized Energy
1.0
0.8
0.6
0.4
0.2
0.8
0.6
0.4
0.2
0.0
0.0
0
Vdd
Vdd
104
105
106
Quality
Gate Capacitance
C g = C g / S
C g = C g / S
Drain Current
I D = I D / S
I D = I D .S
Power Dissipation
P = P / S 2
P = P.S
Power Density
P / Area = ( P / Area )
td ' = td / S
Delay
Energy
E'=
1
P td P.td
=
=
E
S2 S
S3
S3
Ajit Pal, IIT Kharagpur
P / Area = S 3 P / Area
t ' d = td / S 2
E '= E / S
107
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109
110
n.k
Ans: Clock frequency = kf, speedup = S k =
k + (n 1)
111
112
113
114
115
116
117
118
119
120
P1
No voltage or
frequency
Time
T2
(b)
0.25
WORKLOAD 50%
scaling
Relative
Power
Relative
Power
0.5
WORKLOAD 50%
Relative
Power
P2
WORKLOAD 50%
Frequency Scaling 50%
With voltage scaling
P3
0
Time
T1
(c)
Time
(d)
T1
121
DC / DC
fixed
Monitor
Converter
V (r)
Frequency
Generator
f (r)
Workload
Variable Voltage
Processor ( r )
Task
Queue
Ajit Pal, IIT Kharagpur
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128
129
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131
132
Gray code
Transitions
000
001
001
010
011
2
1
011
010
1
1
100
110
101
111
110
101
Total
12
8
Ajit Pal, IIT Kharagpur
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136
137
138
139
S_2
S_1
A
+
B
AS
A
0
CLK
B
Ajit Pal, IIT Kharagpur
S_2
CLK
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141
142
S1
S2
0/0
S3
0/0
S5
S4
0/0
0/0,1/1
143
1/0
0/0
State
Encoding
S1
1/0
S2
0/0
S3
0/0
1/0
S5
S4
0/0
0/0,1/1
S1
000
S2
111
Transitions
Assignment-1
Assignment-2
S3
001
S1
S1
0.0
0.0
S4
110
S1
S2
1.5
0.5
S5
101
S2
S1
1.5
0.5
S2
S3
1.0
0.5
State
Encoding
S3
S1
0.5
1.0
S1
000
S3
S4
1.5
0.5
S2
001
S4
S1
1.0
0.5
S3
011
S4
S5
1.0
1.0
S4
010
S5
S1
2.0
1.0
S5
100
Total
10.0
5.5
145
0/0
s1
0/0
0/0
1/0
s3
s2
s4
1/0
1/0
PS
S1
S2
S3
S4
y2y1
00
01
10
11
x =0
00,0
10,0
11,0
00,0
Y2Y1, z
X=1
01,0
01,0
01,0
01,1
Ajit Pal, IIT Kharagpur
1/1
0/0
146
y1
Y2 = x(y2y1 + y2y1)
Y1 = x + xy2y1
z = xy2y1
y2
Y2
Y1
QD
QD
CLK
147
148
149
Topology 2
A
B
C
ABC
0 1 0
O1
O
2
1 1 1
O1
O2
t=0
A
B
C
D
O1
O2
O3
Realization of A.B.C.D in
cascaded form where there is
possibility of glitch.
A
B
C
D
Ref: D. Samanta, Ajit Pal, Logic Styles for High Performance and Low
Power, Proceedings of the 12th International Workshop on Logic and
Synthesis, 2003 (IWLS-2003), pp. 355-362, May 2003
Advantages
Ease of fabrication
Good noise margin
Robust
Lower switching activity
Good input/output decoupling
No charge sharing problem
Availability of matured logic
synthesis tools and techniques
VDD
pull
up
network
INPUT
f
pull
down
network
VSS
CL
Disadvantages
Larger number of transistors
(larger chip area and delay)
Spurious transitions (glitch)
due to finite propagation delays
leading to extra power
dissipation and incorrect
operation
Short circuit power dissipation
Weak output driving capability
Large number of standard cells
requiring substantial
engineering effort for
technology mapping
Advantages
Combines the advantages
of low power of static
CMOS and low chip area of
pseudo-nMOS
Reduced number of
transistors compared to
static CMOS (n+2 versus
2n)
Faster than static CMOS
logic
No short circuit power
dissipation
No spurious transition and
glitching power dissipation
INPUT
pull
down
network
precharge evaluation
CL
f
f
H|H L
=1
H
=0
VSS
Disadvantages
Higher switching activity
Not as robust as static CMOS
logic
Clock skew problem in
cascaded realization
Suffers from charge sharing
problem
Mature synthesis tool not
available
Disadvantages
Increased delay due to long
chain pf pass-transistors
Multi-threshold voltage
drop
Dual-rail logic to provide all
signals in complementary
form
There is possibility of
sneak path
159
161
Ajit Pal, IIT Kharagpur
0V
2.3V
89mV
0V
0V
34mV
0V
14mV
Leakage
Current (nA)
Leaking
Transistors
000
0.095
Q1, Q2, Q3
001
010
011
100
101
110
111
0.195
0.195
1.874
0.184
1.220
1.140
9.410
Q1,Q2
Q1,Q3
Q1
Q2,Q3
Q2
Q3
Q4,Q5,Q6
164
165
166
167
168
169
170
171
172
Po
ower (W)
Q2. How can you combine power gating with dynamic voltage
scaling to reduce power dissipation?
Ans: As the supply voltage along the
frequency is lowered using the DVFS,
1.0
the supply voltage hits the lower limit
Traditional power
0 . 75
and the curve flattens out and the
management
supply voltage cannot be further
lowered. At this point it is more efficient 0 . 5
DVFS
to switch over to traditional power
0.25
management, i.e. the supply voltage is
DVFS with traditional
power managent
turned on and off depending on the
0
performance requirement. This is how
1.0
0.5
0 . 75
0.25
Normal
Activity level
one can combine the DVFS and
traditional power management approach
as shown in the diagram.
Ajit Pal, IIT Kharagpur
173
174
175
176
177
178
179
180
181
VA
OR
Y
NOR
Y
X
Y
Ajit Pal, IIT Kharagpur
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184
185
186
187
188
189
190
Dynamic
Power
Benefit
Large
Static
Power
Benefit
Small
Design
Impact
Small
Small
Small
Large
Small
Little
Low
Medium
DVFS
Large
Small
Medium
Large
Medium
Multi-Vt
Small
Large
Medium
Small
Medium
Power
Gating
Small
Very
Large
Medium
Large
Medium
Clock
Gating
Multi-Vdd
Verification Implementation
Impact
Impact
192
193
194
195
196
197
198
Thanks!
199