Solutions to Assignment #3

Chapter 4

2. The given DFG is

(20)

(10)

(10)
D

(5)

(a)The maximum sample rate is limited by the critical path from A B (30 u.t.)

SampleRatemax =

1
Tcritical

1
30

(b) The fundamental limit on the sample period is determined by the iteration
bound as follows:
A B C A with two delays
B C D B with one delay

40 25
SamplePeriod limited = TIBound = max , = 25 u.t.
2 1
(c) The manually retimed circuit after applying cutset retiming along edges
{ A B, C A} and {D B, B C , C A}
is given by
D
(20)

(10)
D

(10)

(5)

3. The 4-level pipelined all pass 8th order IIR digital filter DFG is given by
A1

IN

A3

M1

M3

M2

M4

OUT

4D

4D
A4

A2

(a) The iteration bound for the circuit is determined with the cycles
A3 M 4 A3 with four delays
A1 A3 M 3 A4 M 2 A1

with four delays

3 7 7
TIBound = max , = u.t.
4 4 4
(b) The critical path time is from M 2 A1 A3 M 3 A4 with a
Tcritical = 7 u.t.
Assuming each multiply requires 2 u.t. and each add requires 1u.t.

(c) Applying successive node retiming, we get the retimed circuit as

IN

A1

A3

D
D
D

M1

M3

2D
D

M2

M4

OUT

3D
A2

3D
A4

5. The 4th order IIR digital filter implemented as a cascade of 2 2nd-order sections is given
by the circuit
A2

M1

A6

A4

A8

D
M3

M2

A3

A1

M6

A5

M7
A7

D
M4

M8

M5

M9

(a) The two critical paths are given by

M 4 A1 A2 A4 A6 A8 = 7 u.t.

M 2 A1 A2 A4 A6 A8 = 7 u.t.
Tcritical = 7 u.t.
Assuming each multiply requires 2 u.t. and each add requires 1u.t.
The iteration bound for the circuit is determined by the cycles
A2 M 2 A1 A2 with one delay
A2 M 4 A1 A2 with two delays
A6 M 6 A5 A6 with one delay
A6 M 8 A5 A6 with two delays
4 4 4 4
TIBound = max , , , = 4 u.t.
1 2 1 2
(b) The minimum achievable clock period obtained with pipelining and retiming
is the iteration bound of the DFG, is equal to 4 u.t. The retimed and pipelined
circuit is given by
A2

M1

A6

A4

A8

D
M2

M3

A1

A3

D
M4

M5

A5

M6

M7

A7

D
M8

M9

9. The given set of inequalities is

r1 r2 1
r3 r1 3
r4 r1 2
r4 r3 1
r3 r2 1
r5 r1 2
r3 r5 6
r4 r5 2

The constraint graph for this set of inequalities is given by

0
0
s

0
2

1
1
1

0
2

-1
3
-2
-6
5

(a)Using Bellman-Ford algorithm we get the value of r 5 (V ) as the shortest path

r k (V )
V=1
V=2
V=3
V=4
V=5
V=s

k=1

k=2
0
0
0
0
0
0

k=3
0
0
-6
-2
0
0

Thus r1 = r2 = 0, r3 = 6, r4 = 7, r5 = 0

k=4
0
0
-6
-7
0
0

k=5
0
0
-6
-7
0
0

0
0
-6
-7
0
0

(b)Using Floyd-Warshall algorithm, the matrices are given by

R (1)

3 2
1
1

6 2
0 0 0

R (3)

4
3

6
6

R (5)

4
3

6
6

5 2
0 3
1

7 0
5 2
4 3
1

7 0

R ( 7)

4
3

6
6

5 2
4 3
1

7 0

R (2)

R (4)

R (6)

4 0 2
1 0 3
1

6 7

0 6 2 0
4 5 2
3 4 3
1

6 7

0 6 7 0
4 5 2
3 4 3
1

6 7

0 6 7 0

Thus we get r1 = r2 = 0, r3 = 6, r4 = 7, r5 = 0 from R (7)

12. The N stage normalized lattice filter is given by

OUT
IN

Module
N

Module
N-1

Module
2

Module
1

MODULE

(a)The critical path time =the minimum clock cycle = 3 X 25 =75 u.t.
(b) The 2-slow transformed and retimed filter structure is given by

OUT
IN

Module
N

2D

Module
N-1

Module
2

OUT

2D

2D

Module
1

2D

D
D

IN

Module
N

Module
N-1

Module
2

Module
1

D
D

The clock period of the retimed filter is 3 u.t. and the sample period is 2 X 3 =6 u.t.