LAPORAN PRAKTIKUM

PERANCANGAN SISTEM DIGITAL

Modul 5
Finite State Machine

Nama

NIM

Jadwal

: , 25 November / 13.00

LABORATORIUM SISTEM DIGITAL

DEPARTEMEN TEKNIK ELEKTRO DAN TEKNOLOGI INFORMASI
FAKULTAS TEKNIK UNIVERSITAS GADJAH MADA
2015

I. Dasar Teori (yang dibawa sebelum praktikum dan diacc asisten, jadi
gak usah ngeprint lagi)
FPGA adalah bla bla bla..

II. Hasil Praktikum

1. Pembuatan kode verilog Decoder Seven Segment

module fsmvm(oBotol,oKembalian,
iKoin,iSelesai,iClock);
input iClock, iSelesai;
input [1:0] iKoin;
output reg oBotol;
output reg [1:0] oKembalian;
reg [3:0] state = S1;
reg [1:0] SisaUang =0;
reg StatusBotol =0;
parameter S1=0, S2=1, S3=2, S4=3, S5=4, S6=5, S7=6, S8=7, S9=8;
parameter NOL = 0, LIMARATUS = 1, SERIBU = 2;
parameter TUTUP = 0, BUKA =1;
assign outstate = state;
always@(posedge iClock, negedge iSelesai)
begin
if(iSelesai == 1'b0)
begin
oKembalian <= SisaUang;
oBotol <= StatusBotol;
state<=S1;
end
else
begin
case(state)
S1:
begin
case (iKoin)
2'b11: state <= S1;
2'b10: state <= S3;

2'b01: state <= S2;

default: state <= S1;
endcase
end
S2:
begin
case (iKoin)
2'b11: state <= S2;
2'b10: state <= S4;
2'b01: state <= S5;
default: state <= S2;
endcase
end
S3:
begin
case (iKoin)
2'b11: state <= S3;
2'b10: state <= S6;
2'b01: state <= S7;
default: state <= S3;
endcase
end
S4:
begin
case (iKoin)
2'b11: state <= S1;
default: state <= S4;
endcase
end
S5:
begin
case (iKoin)
2'b11: state <= S3;
default: state <= S5;
endcase
end
S6:
begin
case (iKoin)
2'b11: state <= S6;
2'b10: state <= S8;
2'b01: state <= S9;
default: state <= S6;
endcase
end
S7:
begin
case (iKoin)
2'b11: state <= S1;
default: state <= S7;
endcase
end
S8:
begin
case (iKoin)
2'b11: state <= S1;
default: state <= S8;
endcase
end
S9:
begin
case (iKoin)

2'b11: state <= S3;

default: state <= S9;
endcase
end
default: state <=S1;
endcase
end
end
always@(state)
begin
case(state)
S1:begin
SisaUang <= NOL;
StatusBotol <= TUTUP;
end
S2:begin
SisaUang <= SERIBU;
StatusBotol <= TUTUP;
end
S3:begin
SisaUang <= LIMARATUS;
StatusBotol <= TUTUP;
end
S4:begin
SisaUang <= NOL;
StatusBotol <= BUKA;
end
S5:begin
SisaUang <= LIMARATUS;
StatusBotol <= BUKA;
end
S6:begin
SisaUang <= SERIBU;
StatusBotol <= TUTUP;
end
S7:begin
SisaUang <= NOL;
StatusBotol <= BUKA;
end
S8:begin
SisaUang <= NOL;
StatusBotol <= BUKA;
end
S9:begin
SisaUang <= LIMARATUS;
StatusBotol <= BUKA;
end
default : begin
SisaUang <= NOL;
StatusBotol <= TUTUP;
end
endcase
end
endmodule

2. Tugas Lab
Kode verilog decoder 2 bit 4 digit:

module bit2bcd (iKembalian, seg0,seg1,seg2,seg3);

input [1:0] iKembalian;
output reg [3:0] seg0,seg1,seg2,seg3;
always @(iKembalian)
begin
case (iKembalian)
2'b00:
begin
seg0 = 4'h0;
seg1 = 4'h0;
seg2 = 4'h0;
seg3 = 4'h0;
end
2'b01:
begin
seg0 = 4'h0;
seg1 = 4'h0;
seg2 = 4'h5;
seg3 = 4'h0;
end
2'b10:
begin
seg0 = 4'h0;
seg1 = 4'h0;
seg2 = 4'h0;
seg3 = 4'h1;
end
2'b11:
begin
seg0 = 4'h0;
seg1 = 4'h0;
seg2 = 4'h0;
seg3 = 4'h0;
end
endcase
end
endmodule

Decoder seven segmen:

module decoder7segment(segment,counter); //behavioral

input [3:0] counter;
output reg [7:0] segment;

always@(counter)
begin
case(counter)
//urutan segment : DP,D[6],D[5],D[4],D[3],D[2],D[1],D[0]
4'b0000 : segment = 8'b11000000; //0
4'b0001 : segment = 8'b11111001; //1
4'b0010 : segment = 8'b10100100; //2
4'b0011 : segment = 8'b10110000; //3
4'b0100 : segment = 8'b10011001; //4
4'b0101 : segment = 8'b10010010; //5
4'b0110 : segment = 8'b10000010; //6
4'b0111 : segment = 8'b11111000; //7
4'b1000 : segment = 8'b10000000; //8
4'b1001 : segment = 8'b10010000; //9
4'b1010 : segment = 8'b10001000; //a
4'b1011 : segment = 8'b10000011; //b
4'b1100 : segment = 8'b11000110; //c
4'b1101 : segment = 8'b10100001; //d
4'b1110 : segment = 8'b10000110; //e
4'b1111 : segment = 8'b10001110; //f
default : segment = 8'b11111111; //mati
endcase
end
endmodule

III. Pembahasan Hasil Praktikum

Dari hasil praktikum bla bla bla

IV. Kesimpulan

Kesimpulannya
Kesimpulannya