Modern Digital Electronics

Lectureter : Xie Songyun

Chapter4 Digital Logic Familiees

4.1
4.2
4.3
4.4
4.5
4.6

Introduction
Transistor-transistor Logic (TTL)
Characteristics of Digital ICs
MOS Logic
CMOS Logic
Interfacing of CMOS and TTL

4.1 Introduction
Glossary
1. DCTL (Direct-coupled transistor logic)
A form of bipolar logic that uses direct
coupling.
2. I2L (Integrated-injection logic) :
A form of bipolar logic circuit that uses only bipolar
transistors. It is an alternative form of DCTL.
3. DTL (Diode transistor logic)
A form of bipolar logic circuit that uses diodes and
bipolar junction transistors to realize a logic operation.

4.1 Introduction
Glossary
4. HTL (High-threshold logic):A form of
bipolar logic circuit which is identical to DTL but has
appreciably higher noise margins.
5. TTL(Transistor-transistor logic)
: A form of bipolar logic circuit that usees
transistors to realize the logic operations.
6. CMOS (Complementary metal-oxide
semiconductor) : A MOS
device that uses one p-channel one n-channel device to
make an inverter circuit.

4.1 Introduction
The

logic Gates is digital integrated circuits

to realize the logic operations.
There are two types of Semiconductor devices:
bipolar and unipolar.
There are two types of operations in bipolar ICs:
Saturated and Non-saturated .
Saturated bipolar logic families:
RTL, I2L, DCTL, DTL, HTL, TTL
Non-saturated bipolar logic families:
Schottky TTL, and Emitter-coupled (ECL)
Unipolar logic families:
PMOS, NMOS and CMOS

4.1 Introduction
4.1.1 AND Gate
F A B
The

relationship of the
voltage between output F
and inputs AB
5V

Assume:
High level: 1
Low level: 0

0V 3V 0V

0
0

0
1

0
0

3V 0V 0V
3V 3V 3V

1
1

0
1

0
1

A B
0V 0V

F
0V

4.1 Introduction
4.1.2 OR Gate
F=A+B

The

relationship of the
voltage between output F
and inputs AB :
A

Stipulate:
High level: 1
Low level: 0

F A
0
0V 0V 0V
0V 3V 3V 0
3V 0V 3V 1
3V 3V 3V 1

B
0
1
0
1

0
1
1
1

Positive Logic and Negative Logic

Positive

logic: 1-high level,0-low level.

Negative logic: 1-low level, 0-high level.
If the same circuit is analyzed by different logics,
the result will be totally different.

Example: The diode AND Gate circuit

positive logic:

negative logic

positive AND negative OR

negative AND = Positive OR

They are two different

names for the same logic.

NPNNMOS tubes, analyzed with positive source and logic.

PNPCMOS tubes, analyzed with negative source and logic.

4.1 Introduction
4.1.3 NAND Gate
FA

A F
0

(1) NAND Gate

4.1.4 NAND Gate F A B AB
An

NAND Gate is composed of

diode AND Gate and inverter.

The operation order of NAND

Gate: fist AND then NOT

4.1.5 NOR Gate

Gate is
composed of
diode OR Gate
and inverter.
NOT

F A B
The

operation order of NOR

Gate: first OR then NOT

4.2 Transistor-transistor Logic (TTL)

Glossary
1. Active pull-up : A circuit with active
devices used to pull up the output voltage of a
t PHLin response tot the
logic circuit from LOW to HIGH
PLH
appropriate inputs.
2. Totem-pole output : Same as the
active pull-up.
3. Wire-ANDing : Tying the outputs of two or
more gates together to perform additional logic.
Also known as Wired-Logic

4.2 Transistor-transistor Logic (TTL)

Main Poins
The operation and Characteristics of TTL

4.2 Transistor-transistor Logic (TTL)

4.2 Transistor-transistor Logic (TTL)

4.2.1 Operation of TTL NAND Gate
Input part is composed of T1 and

R1.T1 is multi-emitter transistor.

Logical AND is realized by emitter.
Inversion part is composed of

T2 andR2R3. f T2 works as an
inverter. Collector and emitter
provide converse signals
simultaneously to T3 and T4.

input
invert output
Output part is composed of T3T4D4 and R4.T3 and T4 take
turns to turn on with the input signal. If one of them is on, the other
is cutoff. It is active pull-up output .
The function of clamping diode: Protect the circuit when minus
pulse inputs, the current flows to the emitter of T1 is too large.

4.2.1 Operation of TTL NAND Gate

Introduction of Multi-Emitter Transistor

The

structure of multi-emitter transistor is almost the

same as general transistor, the only difference is that
there are more emitters in multi-emitter transistors.
It

is the same function to connect three bases b

and collectors c transistor together.

eA eB eC

n
p

eA
eB
eC

A
B
C

4.2.1 Operation of TTL NAND Gate

Condition 1: At least one input is LOW(0.3V)
The emitter-base junction of T1 is forward-biased.

Vb1= VIL+ Vbe1 = 0.3+0.7= 1V

i b1
1V

Both of T2 and T3 are off.

0.4V

i b2 i c1 0
T1 works in deep saturation state.
Vc1 = VIL + VCes1=0.3+0.1=0.4V
Vc2 = 5V

T2 cuts off

T4D4 turn on, VO VCC Or with load:

VO = VCC - i

B3R2

Vbe3 VD4 = 5 - 0.7 - 0.7 = 3.6 V

If there is one input is low level, the output is high level.

4.2.1 Operation of TTL NAND Gate

Condition 2: All inputs are high (3.6v)
The collector-base junction of T1,
The emitter-base junctions of T2T3
are forward-biased and are on.

Vb1= Vbc1+ Vbe2 + Vbe3 = 3X 0.7 = 2.1V

i
b1

The emitter-base junctions of T1 are

reverse-biased.
T2
T3
ground,
i b1 T1
T2T3 saturate and turn on.

Vc2 = Vces2 + Vbes3 = 0.3+0.7=1V

Vc2 = 1V cant drive T4 & D4 simultaneously T4D4 cut off.

VO = Vces3 = 0.3V

TTL NAND Gateall the inputs are

high level, output is low level.

ic

4.2.1 Operation of TTL NAND Gate

/ mA

120

100

VCC

80
60

Condition 403: Under condition 2 when

20
one of the inputs
suddenly goes to 0v.
io= 0

R1

(+5V)
RC

vce / mA
The corresponding
emitter-base
0
junction of T1 starts
conduction.
VB1
1v(0.9v).
T2 and T3 will be turned off when the
stored base charge is removed.
VC1=VB2=1.4v
T1 operate in the normal active region:

T1

T2

3.6V

i c1 = i b1 = - i b2

This large collector current of T1 is in a direction which

helps in the removal of stored base charge in T2 and T3. It
improves the speed of circuit
The advantages of multi-emitter transistor:

Supplies very large reverse dispersion current to T2T2 and T3

gets into cut-off from saturation soon.

4.8 Transistor-transistor Logic (TTL)

VCC

Condition 3: After T2 is cut off

i B1is very large i b2 i c1 0

R1

(+5V)
RC

Analyze the curves of output

character of the transistor:
ic

T1

T2

/ mA
120
100

3.6V

80
60
40
20

io= 0
O

vce / mA

The emitter of transistor

collector

T1 should work at
deep saturation state.
The voltage drop of saturation
is

Vces1=0.1V

The Disadvantages of Multi-emitter:

invertparasitic transistor effect

ib

(1invert
If all the inputs are 3.6VT2 is saturated
Vb1= Vbc1+ Vbes2 = 0.7 + 0.7 = 1.4V
Ve1=3.6V
Vc1= Vbes2=0.7V
Vb1 < Ve1 the emitter of T1 anti-biases

i IH=Ii b1

Vb1 > Vc1 the collector of T1 biases positively

T1 uses emitter as collector. It is called invert.

Because the blend density of emit area is high, the
The feature blend density of collect area is low, when T is
1
of invert:
used inverted, the magnification is small. I 0.2
The emitter current of T1 is collector current after inverting. i
IH=Ii b1 is pull current load of high level output from the former
level, it is also called input leak current.

2Parasitic Transistor Effect

b
Two emitters formed parasitic transistor of
P
NPN type through base area.
N
N
The emitter connects with high level and
c
low level will form parasitic transistor current, +and the current flows from high level to low
Base
level. current i b flows to low level input ends.
The relationship between base and emitter is called: crosscurrent magnification factordenoted withj .j 0.05
The emitter connected to high level is equal to the
collector of parasitic transistor, the current is i IH=j i b
All in allNo matter is used in the form of invert or parasitic
transistor effect, there are both input leak current and cross leak
current in the input end which is connected to high level. All of the
leak current is i IH =j Ii b. which is pull-current load of
former gate.

4.2.2 Active Poll-up

The TTL NAND gate uses push-draw on output. Two

tubes pass in turnMoreover no matter it is in on or off

state, it presents the low impedance.
EXTwo out-ports of TTL NAND gate are Wired-

AND.

F1 = VOH , F2 = VOL

The loading current passVCCR4T3D4T4place

This current is 3 ~ 40 m A, and the result will damaged T3

and T4 triode Therefore the out-port cannot be WiredAND.
This current spike generates noise in the power

supply distribution system and increases power

dissipation in the gate, more so when it is operated at
high frequencies.

4.2.3 Wired-AND
Wired-AND connection must not used for totem-pole
output circuits because of the current spike problem.
When A or B is high level ,F is low level.
Only when both A and B are low levels ,F is high level.
V CC

V CL

A B F
0 0 1

0 1 0
V CC

V CL

1 0 0
1 1 0

F A B A B

4.2.4 Open-Collector output

Reduce R4,T4 and D4 on the basic of TTL
and the invert gate, making T3tube collector
openConnect the external source power and
the pull resistances when use it.
Can the OC gate perform NAND function?
When there is at least a 0 in A and
Bthen T2 and T3 stop and VO=1
When both A and B are 1 and T2 and T3 saturate,VO=0

VO AB

If we can choose R and the source power

reasonably, the output level can be guaranteed to
reasonable, and the loading current will not very big .
The logic expression of OC gate
The output ends of OC gate can be paralleled ,the lineand function can be performed.

F AB CD AB CD

Problems:P135: 4.13 4.17