LOVELY PROFESSIONAL UNIVERSITY

MODEL HOME WORK: #2

ADVANCE COMPUTER ARCHITECTURE

School: LSM Department:

CSE/IT

Name of the faculty member: Pency

Class: MBA Term: 2nd SEM Section:

S1906 Batch: G0

Max. Marks: 7 DOA: 08/2/2011 DOS:

14/2/2011

Part - A

Ques1. Write the design objective of memory hierarchy in parallel processing

system and a multiprogrammed uniprocessor system. Classify the memory in
hierarchy according to the two most common attributes such as accessing method
and speed.

Ques2. Suppose you are given a processor with cache size of 2K (2048) words
with 16 words per block. Thus the cache has 128 block frames. Let the main
memory have a capacity of 256K words or 16,384 blocks. The physical address is
representable in 18 bits. Implement the direct mapping function in organizing the
cache memory.
Part - B
Ques3. Differentiate between Tse-yun Feng and Wolfgang Handler of processors?
Ques4. For a pipeline with 'n' stages, what is the ideal throughput? What prevents
us from achieving this ideal throughput?

Instrn Throughput
• Pipelining increases processor performance by increasing the instruction
throughput
• Several instructions overlapped in the pipeline, cycle time can be reduced,
increasing the rate at which instructions execute

The ideal throughput is to have 100% delivery through the pipes and it is not possible due to
absorbing and leakages in the pipe.
With "n" stage pipeline the throughput should be "n" instructions.As the pipe stages can't be perfectly
balanced ( time to perform task in a pipeline stage), furthermore pipeline does involve some
overheads.

Ques5. Instead of just 5-to-8 pipe, pipe stages, why not have, say, a pipeline with
50 pipe stages?

Ques6. “OS provides an illusion of more memory than is physically available.”

This statement reflects the key idea of virtual memory. Now some questions arise
in one's mind and answer those questions
which are mentioned as follow:
a) When should pages in memory be replaced?
b) When should pages be put on disk?
c) Write the potential requirements for virtual memory intuition.