University Institute of

Engineering
DEPARTMENT OF COMPUTER
SCIENCE & ENGINEERING
Bachelor of Engineering (Computer Science
& Engineering)
Subject Name: Computer Organization &
Architecture
Subject Code: CST-203/ITT-203

INTERNAL CHIP DISCOVER . LEARN .

ORGANIZATION EMPOWER
 CHAPTER 3

COMPUTER
ORGANIZATION

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 TOPICS TO BE COVERED

• Internal Chip Organization

• Applications of internal level chip organization

• Required improvements

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 LECTURE 1.3.4 (INTERNAL
CHIP ORGANIZATION)
• A memory consists of cells in the form of an array, in which
each cell is capable of storing one bit of information.
• Each row of the cells constitutes a memory words and all
cells of a row are connected to a common line referred to as a
word line.
• Thus W×b memory has w words, each word having ‘b’
number of bits.

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MEMORY CHIP

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 ABOUT MEMORY CHIP

• This is the memory component which shows basic chip organization.

• There are some address connections, chip select input, output enable,
output connections.
• Chip is active low i.e it will be enabled if low input (0) is given.
• Write an read lines are also active low.
• OE stands for Output Enable, WE stands for Write Enable.
• For chip to be in working condition, Chip must be given active low
input.

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 APPLICATIONS

• Computer organization and architecture course deals with instruction set architecture,

micro architecture and efficient implementation of micro architecture.

• Understanding the computer architecture concepts is essential for students interested

in hardware, processor design, compilers, and operating systems. 

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 IMPROVEMENTS IN CHIP
ORGANIZATION AND ARCHITECTURE

• There are three approaches to achieving increased processor speed:

• Increase the hardware speed of the processor.

• Increase the size and speed of caches that are interposed between the processor and

main memory. In particular, by dedicating a portion of the processor chip itself to the

cache, cache access times drop significantly.

• Make changes to the processor organization and architecture that increase the

effective speed of instruction execution.

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 IMPROVEMENTS IN CHIP
ORGANIZATION AND ARCHITECTURE

However, as clock speed and logic density increase, a number of obstacles become more

significant:

• Power: As the density of logic and the clock speed on a chip increase, so does the power

density.

• RC delay: The speed at which electrons can flow on a chip between transistors is limited by the

resistance and capacitance of the metal wires connecting them; specifically, delay increases as

the RC product increases. As components on the chip decrease in size, the wire interconnects

become thinner, increasing resistance. Also, the wires are closer together, increasing

capacitance.

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 IMPROVEMENTS IN CHIP
ORGANIZATION AND ARCHITECTURE

• Memory latency: Memory speeds lag processor speeds. Beginning in the

late 1980s, and continuing for about 15 years, two main strategies have

been used to increase performance beyond what can be achieved simply by

increasing clock speed. First, there has been an increase in cache capacity.

Second, the instruction execution logic within a processor has become

increasingly complex to enable parallel execution of instructions within the

processor.

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 HOMEWORK
Q1. The parallel mode of communication is not suitable for long devices because of ______
A. Timing skew
B. Memory access delay
C. Latency
D. None of the mentioned

 Q2. User programmable terminals that combine VDT hardware with built-in microprocessor is _____
A. KIPs
B. Pc
C. Mainframe
D. Intelligent terminals

Q3. The use of spooler programs or _______ Hardware allows PC operators to do the processing work
at the same time a printing operation is in progress.
A. Registers
B. Memory
C. Buffer
D.CPU
• Answers:1.A,2.D,3.C

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 REFERENCES
Reference Books:
1. J.P. Hayes, “Computer Architecture and Organization”, Third Edition.
2. Mano, M., “Computer System Architecture”, Third Edition, Prentice Hall.
3. Stallings, W., “Computer Organization and Architecture”, Eighth Edition, Pearson
Education.
Text Books:
4. Carpinelli J.D,” Computer systems organization &Architecture”, Fourth Edition,
Addison Wesley.
5. Patterson and Hennessy, “Computer Architecture” , Fifth Edition Morgaon Kauffman.
Reference Website
6. https://www.geeksforgeeks.org/computer-organization-and-architecture-tutorials/
7. https://www.slideshare.net/ishapadhy/memory-organization-73277070
8. https://upscfever.com/upsc-fever/en/gatecse/en-gatecse-chp166.html
 

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THANK YOU