“Evolution and Performance”

in
[ Microprocessor Systems and Assembly
Language ]

Lecture-03

Maham Fatima
mahamfatima@cuisahiwal.edu.pk
 [ Topics Covered ]
• Computer Evolution
– Performance mismatch

– Improvement in chip organization and architecture

Note: Topics covered are from chapter 3 of William Stallings book.

1.2
 [ Brief History of Computers ]

Reducing Distance between Components

Decreasing Component Size
Increasing Memory Size
Increasing Processor Speed
Balancing the performance of various elements
(Changing Organization of the Processor)
“pipelining and parallel execution techniques”
“what’s the benefit of it????”

1.3
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 To Balance out the Mismatch between Elements,
the Design must handle with the Evolving Factors:

1. Performance improvement in various components differ

greatly from one type of element to another.

2. New application and new peripherals constantly change the

nature of the demand on the system w.r.t. instruction profile
and data access patterns. → this statement is difficult to comprehend at
this stage, but certainly it doesn’t apply to all.

1.6
 Improvement in Chip Organization and Architecture
AND
Challenge of Balancing of Processor Performance
with that of Main Memory & other Components

1. Increase in Hardware Speed of Processor

reducing size of logic gates → increases logic density → reducing
propagation delay

2. An increase in Clock Rate

causes operations to execute more rapidly

1.7
 Improvement in Chip Organization and Architecture
AND
Challenge of Balancing of Processor Performance
with that of Main Memory & other Components

Issues with the previous two improvements:

a) Power Density increases
High heat dissipation → bottlenecks/limits further improvement.
b) RC Delay increases
Speed of the electrons’ flow on a chip between transistors is limited by RC product.
R: As component size decreases on chip, the wire interconnects become thinner,
increasing resistance.
C: As the wires are closer together, increasing capacitance.

1.8
 Improvement in Chip Organization and Architecture
AND
Challenge of Balancing of Processor Performance
with that of Main Memory & other Components

3. Increase the number of bits that are retrieved at one time.

e.g., 8-bit, 16-bit, 32-bit or 64-bit data processing.

4. Cache Capacity (1, 2 or 3 levels), w.r.t. Size and Speed.

Original Pentium has devoted 10% of Cache and P4 almost half of chip area
to Cache.

1.9
 Improvement in Chip Organization and Architecture
AND
Challenge of Balancing of Processor Performance
with that of Main Memory & other Components

5. Instruction execution logic becomes more complex by

introducing parallel processing (pipelining and superscalar).

Pipelining: It enables different stages of execution of different instructions to

occur at the same time along the pipeline.

Superscalar: It allows multiple pipelines within a single processor so that

instructions that do not depend on one another can be executed in parallel.

1.10
 Improvement in Chip Organization and Architecture
AND
Challenge of Balancing of Processor Performance
with that of Main Memory & other Components

6. Placing Multiple Processors on a Single Chip, called Multiple

Core or Multicore, with large shared Cache.
If the software can support the effective use of multiple processors, then
doubling the number of processors almost doubles performance.

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 Intel x86 Architecture Evolution
8080 Pentium Core
(8-bit) (Parallel Processing) (2 Processors on a
Single Chip)
8086 Pentium Pro Core 2
(16-bit) (More Powerful) (64-bit)
80286 Pentium II Core 2 Quad
(Enabled 16-bit Memory (MMX Technology) (4 Processors on a
Addressing) Single Chip)
80386 Pentium III
(32-bit, Multi-tasking) (3D Graphics SW)
80486 Pentium 4
(Instruction Pipelining, (Enhancements for
Math Coprocessor) Multimedia)

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