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INTRODUCTION: This report contains the lot average results obtained by MOSIS
from measurements of MOSIS test structures on each wafer of
this fabrication lot. SPICE parameters obtained from similar
measurements on a selected wafer are also attached.
MINIMUM 0.36/0.24
Vth 0.53 -0.52 volts
SHORT 20.0/0.24
Idss 594 -270 uA/um
Vth 0.51 -0.54 volts
Vpt 7.3 -7.3 volts
WIDE 20.0/0.24
Ids0 5.2 < 2.5 pA/um
LARGE 50/50
Vth 0.43 -0.59 volts
Vjbkd 4.8 -6.4 volts
Ijlk <50.0 <50.0 pA
Gamma 0.43 0.61 V^0.5
COMMENTS: Poly bias varies with design technology. To account for mask
bias use the appropriate value for the parameters XL and XW
in your SPICE model card.
Design Technology XL (um) XW (um)
----------------- ------- ------
SCN5M_DEEP (lambda=0.12) 0.00 -0.04
thick oxide, NMOS -0.01 -0.04
thick oxide, PMOS -0.06
SCN6M_SUBM (lambda=0.15) -0.06 0.00
thick oxide, NMOS -0.10 0.00
thick oxide, PMOS -0.15
COMMENTS: DEEP_SUBMICRON
V01Z SPICE BSIM3 VERSION 3.1 PARAMETERS