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INA105
FEATURES APPLICATIONS
● CMR 86dB min OVER TEMPERATURE ● DIFFERENTIAL AMPLIFIER
● GAIN ERROR: 0.01% max ● INSTRUMENTATION AMPLIFIER
● NONLINEARITY: 0.001% max BUILDING BLOCK
● NO EXTERNAL ADJUSTMENTS ● UNITY-GAIN INVERTING AMPLIFIER
REQUIRED ● GAIN-OF-1/2 AMPLIFIER
● EASY TO USE ● NONINVERTING GAIN-OF-2 AMPLIFIER
● COMPLETE SOLUTION ● AVERAGE VALUE AMPLIFIER
● HIGHLY VERSATILE ● ABSOLUTE VALUE AMPLIFIER
● LOW COST ● SUMMING AMPLIFIER
● PLASTIC DIP, TO-99 HERMETIC METAL, ● SYNCHRONOUS DEMODULATOR
AND SO-8 SOIC PACKAGES ● CURRENT RECEIVER WITH COMPLIANCE
TO RAILS
● 4mA TO 20mA TRANSMITTER
● VOLTAGE-CONTROLLED CURRENT
SOURCE
● ALL-PASS FILTERS
DESCRIPTION
The INA105 is a monolithic Gain = 1 differential
amplifier consisting of a precision op amp and on-chip 25kΩ 25kΩ
metal film resistors. The resistors are laser trimmed 2 5
–In Sense
for accurate gain and high common-mode rejection. 7
V+
Excellent TCR tracking of the resistors maintains
gain accuracy and common-mode rejection over 6
Output
temperature. 4
V–
The differential amplifier is the foundation of many 3
25kΩ 25kΩ
1
commonly used circuits. The INA105 provides this +In Ref
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©
1985 Burr-Brown Corporation PDS-617G Printed in U.S.A. August, 1993
SBOS145
SPECIFICATIONS
ELECTRICAL
At +25°C, VCC = ±15V, unless otherwise noted.
GAIN
Initial(1) 1 ✻ ✻ V/V
Error 0.005 0.01 ✻ ✻ 0.01 0.025 %
vs Temperature 1 5 ✻ ✻ ✻ ✻ ppm/°C
Nonlinearity(2) 0.0002 0.001 ✻ ✻ ✻ ✻ %
OUTPUT
Rated Voltage IO = +20mA, –5mA 10 12 ✻ ✻ ✻ ✻ V
Rated Current VO = 10V +20, –5 ✻ ✻ mA
Impedance 0.01 ✻ ✻ Ω
Current Limit To Common +40/–10 ✻ ✻ mA
Capacitive Load Stable Operation 1000 ✻ ✻ pF
INPUT
Impedance(3) Differential 50 ✻ ✻ kΩ
Common-Mode 50 ✻ ✻ kΩ
Voltage Range(4) Differential ±10 ✻ ✻ V
Common-Mode ±20 ✻ ✻ V
Common-Mode Rejection(5) TA = TMIN to TMAX 80 90 86 100 72 ✻ dB
OFFSET VOLTAGE RTO(6), (7)
Initial 50 250 ✻ ✻ ✻ 500 µV
vs Temperature 5 20 5 10 ✻ ✻ µV/°C
vs Supply ±VS = 6V to 18V 1 25 ✻ 15 ✻ ✻ µV/V
vs Time 20 ✻ ✻ µV/mo
OUTPUT NOISE VOLTAGE RTO(6), (8)
fB = 0.01Hz to 10Hz 2.4 ✻ ✻ µVp-p
fO = 10kHz 60 ✻ ✻ nV/√Hz
DYNAMIC RESPONSE
Small Signal Bandwidth –3dB 1 ✻ ✻ MHz
Full Power Bandwidth VO = 20Vp-p 30 50 ✻ ✻ ✻ ✻ kHz
Slew Rate 2 3 ✻ ✻ ✻ ✻ V/µs
Settling Time: 0.1% VO = 10V Step 4 ✻ ✻ µs
0.01% VO = 10V Step 5 ✻ ✻ µs
0.01% VCM = 10V Step, VDIFF = 0V 1.5 ✻ ✻ µs
POWER SUPPLY
Rated ±15 ✻ ✻ V
Voltage Range Derated Performance ±5 ±18 ✻ ✻ ✻ ✻ V
Quiescent Current VO = 0V ±1.5 ±2 ✻ ✻ ✻ ✻ mA
TEMPERATURE RANGE
Specification –40 +85 ✻ ✻ ✻ ✻ °C
Operation –55 +125 ✻ ✻ –40 +85 °C
Storage –65 +150 ✻ ✻ –40 +125 °C
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
INA105 2
PIN CONFIGURATIONS
Top View TO-99 Top View DIP/SOIC
Tab No Internal
Connection
8
Ref V+
1 7
Ref 1 8 No Internal Connection
(1)
–In 2 7 V+
–In 2 6 Output
+In 3 6 Output
V– 4 5 Sense
3 5
+In Sense
4
INA105AM
INA105BM
V– NOTE: (1) Performance grade identifier box for small outline surface mount.
Case internally connected to V–. Make no connection. Blank indicates K grade. Part is marked INA105U.
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
3 INA105
TYPICAL PERFORMANCE CURVES
At TA = 25°C, VS = ±15V, unless otherwise noted.
+50
–50
0 4 8 12 16 0 5 10
Time (µs) Time (µs)
–12.5 VS = ±15V
VOUT (V)
–10 VS = ±12V
0
–7.5
–50 –5
VS = ±5V
–2.5
0 5 10 0
0 –2 –4 –6 –8 –10 –12
Time (µs) –IOUT (mA)
90
VOUT (V)
10 VS = ±12V
7.5 80
5
VS = ±5V 70
2.5
0 60
0 6 12 18 24 30 36 10 100 1k 10k 100k
IOUT (mA) Frequency (Hz)
INA105 4
TYPICAL PERFORMANCE CURVES (CONT)
At TA = 25°C, VS = ±15V, unless otherwise noted.
120 30
100
Negative CMV
V– 18
80 Positive CMV
12
60
V+ 6
40 0
1 10 100 1k 10k 100k ±3 ±6 ±9 ±12 ±15 ±18 ±21
Frequency (Hz) Supply Voltage (V)
APPLICATION INFORMATION V– V+
Figure 1 shows the basic connections required for operation 1µF 1µF
of the INA105. Power supply bypass capacitors should be
connected close to the device pins. 4 7
INA105
The differential input signal is connected to pins 2 and 3 as
shown. The source impedances connected to the inputs must R1 R2
2 5
be nearly equal to assure good common-mode rejection. A V2
5Ω mismatch in source impedance will degrade the com- 25kΩ 25kΩ
mon-mode rejection of a typical device to approximately
80dB. If the source has a known mismatch in source imped- R3 6
3
ance, an additional resistor in series with one input can be V3 VOUT = V3 – V2
used to preserve good common-mode rejection. 25kΩ
5 INA105
INA105 V1
–In INA105
A1
R1 R2
2 5
V2
2 5
R2
6
VO
6
R1
V0
10Ω R3 R2
0utput
3
V3
3 1
R4
+15V A2
V1
1 +In
VO = V3 – V3 499kΩ
Offset Adjustment 100kΩ VO = (1 + 2R2/R1) (V2 –V1)
Range = ±300µV
For low source impedance applications, an input stage using OPA27 op
10Ω
amps will give the best low noise, offset, and temperature drift performance.
–15V At source impedances above about 10kΩ, the bias current noise of the
OPA27 reacting with the input impedance begins to dominate the noise
performance. For these applications, using the OPA111 or dual OPA2111
FET input op amp will provide lower noise performance. For lower cost use
FIGURE 2. Offset Adjustment.
the OPA121 plastic. To construct an electrometer use the OPA128.
6
V0
FIGURE 4. Precision Instrumentation Amplifier.
R3 R4
+In 3 1
V3 INA105
25kΩ 25kΩ
2 5
V0 = V3 – V2 100Ω
Gain Error = 0.005% 1%
CMR = 100dB 6
Nonlinearity = 0.0002% V–
V0
100Ω 0 to 2V
1%
3 1
FIGURE 3. Precision Difference Amplifier.
IIN
0 to 20mA
INA105 6
INA105 INA105
2
2 5
V2
5
6
V0
6
V0
1
V1
V0 = V1
Gain Error = 0.001% maximum
1 3
V0 = – V2 FIGURE 9. Precision Unity-Gain Buffer.
Gain Error = 0.01% maximum
Nonlinearity = 0.001% maximum
Gain Drift = 2ppm/°C
V+ V+
FIGURE 6. Precision Unity-Gain Inverting Amplifier. 3
INA105
2
+15V
2
5
6 +10V Out
7
REF10 6
INA105 (V+)/2
2 5 –10V Out
4
6
1
Common 1 4 Common
3
FIGURE 10. Pseudoground Generator.
6
REF10
+5V Out 6
V0
2 1
V1
INA105
4
5 V3
3
–5V Out
V0 = (V1 + V3)/2, ±0.01% maximum
6
FIGURE 11. Precision Average Value Amplifier.
1 3
7 INA105
INA105
INA105 0 to +10V Output
±2ppm/°C
2
2 5
5
6
V0 6 Output
1 (1)
1
V1 –10V
to
3 +10V
Input
3 Device Output
V 0 = 2 • V1 VFC320 0-10kHz
Gain Error = 0.01% maximum VFC100 0-FCLOCK/2
Gain Drift = 2ppm/°C DAC80 0-FS (12 bits)
2 DAC703 0-FS (16 bits)
FIGURE 12. Precision (G = 2) Amplifier. XTR110 4-20mA
6
REF10
10V
INA105
4
NOTE: (1) Unipolar Input Device.
2 5
V3 R1 R2
3
2 5
INA105
V3
INA105 3
2 For G=10,
(
V0 = 1 +
R2
R1
)( V 1 + V3
2 ) See INA106.
5
FIGURE 16. Precision Summing Amplifier with Gain.
6
V0
3
V3 = 1/2 V3
±20V
1
V0 = V3/2, ±0.01%
INA105 8
Offset
Adjust
6 7 8
Noise (60Hz hum)
INA101AG
3
A1
4
Transducer or
Analog Signal 10kΩ
5 20kΩ 10kΩ
RG A3 Output
1
10
20kΩ 10kΩ
11
A2 10kΩ
12
2 13 9 14 Common
+VCC –VCC
3
INA105
6
1
INA105
2 5
INA105
6 2 5
3
V1
6
V2 V0
1 3
V3
V0 = V3 + V4 – V1 – V2 V4
1
9 INA105
INA105 INA105
2 5
V2
R 2 5
6
R
6
V1 V01
3 1
V1
3 1
IO = (V1 – V2) (1/25k + 1/R)
For R ≅ 200 Ω, Figure 24 will Load IO
provide superior performance.
V2
FIGURE 19. Precision Voltage-to-Current Converter with INA105
Differential Inputs.
2 5
INA105
6
V02
2 5
V2
3 1
6
R
3 V01 – V02 = 2 (V2 – V1)
V3
1
IO = (V3 – V2)/R
IO Load
INA105
2 5
V2
R
3 1
V3
INA105 Gate can be
+VCC –5V
2 5
V2
IO = (V3 – V2)/R
R
Load IO
6
R < 200Ω
3 1 Gate can be
V3 +VS –5V
FIGURE 23. Isolating Current Source with Buffering Ampli-
fier for Greater Accuracy.
INA105 10
Window Center–Window Span
2 5
Window Span
0 to +5V
3 1
Window 8
Center 6
±10V
3
1 INA105
Window Center + Window Span
FIGURE 24. Window Comparator with Window Span and Window Center Inputs.
–In
V1
(1) INA105
V+
R2
2 5
R1 R
6
R2
3
1kΩ R
1
(1)
+In
V2
Load IO
FIGURE 25. Precision Voltage-Controlled Current Source with Buffered Differential Inputs and Gain.
INA105
2 5
V1
DG188 VO
6
3
1
Logic In VO
1 0 –V1
Logic
In 1 +V1
11 INA105
INA105
V1 R2 R2 2
A1
5
R1
49.5Ω
6
V0 = 200 (V2 – V1)
1
R1 A3
R1
49.5Ω
3
R2 R2
A2
V2
Conventional
Instrumentation INA105
Amplifier (e.g., INA101 or INA102) A=2
A = 100
FIGURE 27. Boosting Instrumentation Amplifier Common-Mode Range From ±5 to ±7.5V with 10V Full-Scale Output.
INA105
R1 R2
2 5
10pF
D1
6
R3 V0 = |V1|
3
D2 R4
OPA111
V1 1
Input
R5
2kΩ
12.5kΩ 1kΩ
0 to 10V
In
50kΩ
INA105
OPA27 2 5
+15V
2
50.1Ω
6
6
REF10
10V 50.1Ω
3 1
4
RLOAD
4 to 20mA
Out
INA105 12
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.