VHDL for Latches and Flip-Flops

Gated D Latch
library ieee; use ieee.std_logic_1164.all; ENTITY gated_D IS PORT( D, Clk : IN STD_LOGIC; Q, Qbar : OUT STD_LOGIC); END gated_D; ARCHITECTURE behavioral OF gated_D IS BEGIN PROCESS(D, Clk) BEGIN IF Clk = '1' THEN -- Implied memory Q <= D; Qbar <= not D; END IF; END PROCESS; END behavioral;

Rising Edge Triggered D Flip-Flop

library ieee; use ieee.std_logic_1164.all; ENTITY dff IS PORT( D, Clk, Clr, Pre : IN Q, Qbar END dff;

STD_LOGIC; : OUT STD_LOGIC);

ARCHITECTURE behavioral OF dff IS BEGIN PROCESS(Clk) --We only care about Clk BEGIN IF (Clk'event) AND (Clk='1') THEN -- Positive Edge Q <= D; Qbar <= not D; END IF; END PROCESS; END behavioral;

Rising Edge Triggered D Flip-Flop - alternate

ARCHITECTURE behavioral2 OF dff IS BEGIN PROCESS(Clk) BEGIN WAIT UNTIL Clk='1' Q <= D; Qbar <= not D; END IF; END PROCESS; END behavioral2; --We only care about Clk -- Positive Edge

Rising Edge Triggered D Flip-Flop with Asynchronous Preset and Clear

library ieee; use ieee.std_logic_1164.all; ENTITY dff_asynch IS PORT( D, Clk, Clr, Pre Q, Qbar END dff_asynch;

: IN

STD_LOGIC; : OUT STD_LOGIC);

ARCHITECTURE behavioral OF dff_asynch IS BEGIN PROCESS(D, Clk, Clr, Pre) BEGIN IF Clr = '0' THEN -- Dont wait for clock Q <= '0'; Qbar <= '1'; ELSIF Pre = '0' THEN Q <= '1'; Qbar <= '0'; ELSIF (Clk'event) AND (Clk='1') THEN -- Positive Edge Q <= D; Qbar <= not D; END IF; END PROCESS; END behavioral;