Holy Cross of Davao College Sta.

Ana Avenue, Davao City

FET Biasing: Voltage Divider

Submitted to: Engr. Michael Calamba

Submitted by: Jan Doris Latada Al John Rendon Mark Gerodias Ramil Mosqueda

March 2011

Date Experiment

I. Objectives: 1. To be able to know the advantage and disadvantages of voltage divider bias configuration. 2. To be able to differentiate the operation of voltage divider bias configuration from other biasing configuration. II. Procedure: 1. Det. the Vgs from the Shockley equation or the input characteristics. If the given Vs is less than this Vgs then no value of Rs may be found to satisfy [A], and the problem cannot be solved. 2. From [C] determine the Rs and Rd. 3. From [A] determine a pair of values of R1 and R2. III. Data: 1.Vp = -1V 2.VDD = 10.00 V, Rs = 3.415k Id Vds Vs Vd 3.VDD = 10.00 V, Rs = 626.7 IDSS = 1.1 mA Id = 1.00 mA, Rd = 8.453K Desired 1.00mA 5.00V 3.00V 8.00V Vd = 8.52 V, Rd = 8.45 K Desired 0.95mA 6.00V 1.00V 8.52V Id = 1.00 mA, Vs =3.07V, Vd = 8.52V R1 = 1M R2 = 278.702K Measured 1.02mA 5.0V 3.8V 8.1V Id = 0.95mA, R1 = 855k Measured 0.85mA 5.45V 1.80V 6.20V % Difference 5.25% 5% 25.4% 2.2% Vs=3.00V, Vds=6.0V R2 = 63.532 K % Difference 6.3% 6% 40% 55%

Id Vds Vs Vd

IV. Computation: Vds Vds Rs Rs R2 R2 Vg Vg Rd Rd = Vp (1-Id/Idss) = -1(1-1mA/1.1mA) = -0.0465V = Vg-Vgs/Id = 2.95+0.0465V/1mA = 3.415k = VgR1/Vdd-Vg = 0.53(855k)/12V-2.95V = 50.071K = Vgs + 3 = -0.047 + 3 = 2.95V = Vdd Vds-IdRs/Id = 12V-5V-[1mA (3.415k )]/1mA = 3.585 K

V. Analysis We have analyzed that table1 and table2 have likely the same values. Their Id, Vds, Vs, Vd are closely related to each other. VI. Conclusion: We therefore conclude that the most stable of all biasing configurations is the voltage divider biasing configuration. The voltage divider configuration is independent from the transistor beta, which is temperature sensitive.