Yu Sui, Zhenghong Sun, Yi Wang

What is FinFET

Planar MOSFET[1]

FinFet[2]

Why FinFET
Suppress short channel affect Better in driving current More compact

Figure . FinFET typical layout and schematic cross sectional structures.

Variations of Finfet:
1. tri-gate finfet These transistors employ a single gate stacked on top of two vertical gates allowing for essentially three times the surface area for electrons to travel. 2. Gate-all-around(GAA) FETs Gate-all-around FETs are similar in concept to FinFETs except that the gate material surrounds the channel region on all sides.

http://news.uns.purdue.edu/x/2009b/091110YeFinfets.doc.html

Evaluation of FinFet
The current performance is poor Conducted only in high voltage

Reasons for poor performance

Large pits and holes in the silicon fin and the source

drain areas Fabrication part: photo resist alone is not a sufficient etch mask

Cost of FinFET
The total steps are more than usual MOSFET process, but the cost of material are smaller. Since it is more compact, using FinFET is economical.

Perspective
For future 22nm device, the FinFET is a great trial More tests should be conducted, and better fabrication

technology is needed Inventing new device is always essential to enhance the circuit performance

Reference
[1] Slides from Prof. Robert Dick [2]http://en.wikipedia.org/wiki/File:Doublegate_FinFET.PNG [3]http://en.wikipedia.org/wiki/Multigate_device Design and Fabrication of Tri-Gated FinFET, Mohammed R.Rahman, 22nd Annual Microelectronic Engineering Conference, May 2004 [4]http://news.uns.purdue.edu/x/2009b/091110YeFinfets.doc.ht ml [5] http://www.electroiq.com/index/display/semiconductorsarticle-display/327683/articles/solid-state-technology/volume51/issue-5/features/nanotechnology/fully-gate-all-aroundsilicon-nanowire-cmos-devices.html