Cu hi 1.1: Kin trc my tnh l g ? Kin trc my tnh c cu thnh t nhng thnh phn no ?

K/n : l mt khoa hc v la chn v kt ni cc thnh phn phn cng ca my tnh nhm t c cc yu cu: Hiu nng / tc (performance): nhanh tt Chc nng (functionality): nhiu tnh nng tt Gi thnh (cost): r tt Ba thnh phn c bn ca kin trc my tnh: 1. Kin trc tp lnh (Instruction set architecture - ISA) l hnh nh tru tng ca my tnh mc ngn ng my (hp ng). Kin trc tp lnh gm: Tp lnh Cc ch a ch b nh Cc thanh ghi Cc khun dng a ch v d liu 2. Vi kin trc (microarchitecture), cn c gi l t chc my tnh l m t v h thng mc thp, lin quan n cc vn : Cc thnh phn phn cng ca my tnh kt ni vi nhaunh th no? Cc thnh phn phn cng ca my tnh tng tc vi nhau nh th no thc thi tp lnh? 3. Thit k h thng (System Design) bao gm tt c cc thnh phn phn cng khc trong h thng tnh ton, nh: H thng kt ni nh bus v cc chuyn mch iu khin b nh v qun l phn cp h thng nh Cc c ch gim ti cho CPU nh l DMA Cc vn khc nh a x l.

Cu hi 1.2: Nu s khi chc nng ca h thng my tnh.

Cu hi 1.3: Thanh ghi ca vi x l l g? Nu chc nng v c im ca thanh ghi tch lu A. Thanh ghi (registers) l cc nh bn trong CPU: Lu tr tm thi lnh v d liu cho CPU x l; Kch thc nh; Tc rt cao (bng tc CPU) Cc CPU c (80x86) c 1632 thanh ghi; cc CPU hin i Thanh tch lu A (Accumulator) Thanh tch lu A l mt trong cc thanh ghi quan trng nht ca hu ht cc CPU: A c dng cha ton hng u vo A c dng cha kt qu u ra

CPU: Np cc lnh t b nh v thc thi chng CPU gm c: n v iu khin (CU) n v s hc v l gc (ALU) Cc thanh ghi B nh trong Lu cc lnh v d liu cho CPU x l C loi ROM B nh ch c lu cc lnh v d liu cho h thng RAM B nh truy nhp ngu nhin lu cc lnh v d liu cho h thng v ngi dng Thit b vo: iu khin v nhp d liu Bn phm Chut a My qut Thit b ra: xut d liu Mn hnh My in My v a But h thng Tp hp dy dn ni CPU vi cc b phn khc ca my tnh 3 loi: But a ch (But A) But d liu (But D) But iu khin (But C)

Kch thc ca A bng kch thc t x l ca CPU: 8, 16, 32 v 64 bit. A cng c s dng trao i d liu vi cc thit b vo ra.

Cu hi 1.4: Nu chc nng v c im ca b m chng trnh PC (cn gi l thanh ghi lnh IP). B m chng trnh PC B m chng trnh PC (Program Counter) hoc con tr lnh (IP Instruction Pointer) lun cha a ch ca nh cha lnh c thc hin tip theo;

PC cha a ch ca nh cha lnh u tin ca chng trnh khi n c kch hot v c np vo b nh; Khi CPU thc hin xong lnh, a ch ca nh cha lnh tip theo c np vo PC; Kch thc PC ph thuc vo thit k CPU. Cc kch thc thng dng l 8, 16, 32 v 64 bit.

Cu hi 1.5: Thanh ghi c (hay thanh ghi trng thi) ca vi x l c chc nng g? Nu ngha ca cc c nh (C), c khng (Z), c du (S). Thanh ghi trng thi (SR - Status Register) hoc thanh ghi c (FR Flag Register): mi bt ca FR lu trng thi ca kt qu ca php tnh ALU thc hin; Hai loi bt c: C trng thi: CF, OF, AF, ZF, PF, SF C iu khin: IF, TF, DF Cc bt c thng c s dng nh l cc iu kin trong cc lnh r nhnh to logic chng trnh; Kch thc ca thanh ghi FR ph thuc thit k CPU. ngha ca cc c C, Z, S: ZF: C Zero, ZF=1 nu kt qu=0 v ZF=0 nu kt qu<>0. SF: C du, SF=1 nu kt qu m v SF=0 nu kt qu dng. CF: C nh, CF=1 nu c nh/mn, CF=0 trong trng hp khc. Cu hi 1.6: Ch a ch ca vi x l l g ? M t ch a ch tc th. Cho v d minh ho. Ch a ch (Addressing modes) l phng thc CPU t chc cc ton hng ca lnh. Ch a ch cho php CPU kim tra dng v tm cc ton hng ca lnh. Ch a ch - Tc th Gi tr hng ca ton hng ngun (source operand) nm ngay sau m lnh; Ton hng ch c th l 1 thanh ghi hoc 1 a ch nh; V d: LOAD R1, #1000; R1 1000 Np gi tr 1000 vo thanh ghi R1. LOAD B, #500; M[B] 500 Np gi tr 500 vo nh B.

Cu hi 1.7: Ch a ch ca vi x l l g ? M t ch a ch trc tip. Cho v d minh ho. Ch a ch (Addressing modes) l phng thc CPU t chc cc ton hng ca lnh. Ch a ch cho php CPU kim tra dng v tm cc ton hng ca lnh. Trc tip/tuyt i S dng mt hng biu din a ch mt nh lm mt ton hng; Ton hng cn li c th l 1 thanh ghi hoc 1 a ch nh; V d: LOAD R1, 1000; R1 M[1000] Np ni dung nh c a ch 1000 vo thanh ghi R1. Cu hi 1.8: Ch a ch ca vi x l l g ? M t ch a ch gin tip qua thanh ghi. Cho v d minh ho. Ch a ch (Addressing modes) l phng thc CPU t chc cc ton hng ca lnh. Ch a ch cho php CPU kim tra dng v tm cc ton hng ca lnh. Gin tip qua thanh ghi Trong ch a ch gin tip, mt thanh ghi c s dng lu a ch ton hng. V d: LOAD Rj, (Ri); RjM[Ri] Np ni dung nh c a ch lu trong thanh ghi Ri vo thanh ghi Rj. Cu hi 1.9: Ch a ch ca vi x l l g ? M t ch a ch gin tip qua nh. Cho v d minh ho. Ch a ch (Addressing modes) l phng thc CPU t chc cc ton hng ca lnh. Ch a ch cho php CPU kim tra dng v tm cc ton hng ca lnh. Gin tip qua nh : Trong ch a ch gin tip, mt nh c s dng lu a ch ton hng. V d LOAD Ri, (1000); Ri M[M[1000]] Np ni dung nh c a ch lu trong nh 1000 vo thanh ghi Ri.

Cu hi 1.10: Ch a ch ca vi x l l g ? M t ch a ch ch s. Cho v d minh ho. -Ch a ch (Addressing modes) l phng thc CPU t chc cc ton hng ca lnh. -Ch a ch cho php CPU kim tra dng v tm cc ton hng ca lnh. a ch ch s: a ch ca 1 ton hng c to thnh bi php cng gia 1 hng v thanh ghi ch s (index register); V d: LOAD Ri, X(Rind); RiM[X+Rind] X l hng v Rind l thanh ghi ch s. Cu hi 1.11: Ch a ch ca vi x l l g ? M t ch a ch tng i. Cho v d minh ho. Ch a ch (Addressing modes) l phng thc CPU t chc cc ton hng ca lnh. Ch a ch cho php CPU kim tra dng v tm cc ton hng ca lnh. Da ch tng i : a ch ca 1 ton hng c to thnh bi php cng gia 1 hng v b m chng trnh PC (Program Counter); V d: LOAD Ri, X(PC); RiM[X+PC] X l hng v PC l b m chng trnh. Cu hi 1.12: Nu phng thc trao i d liu gia CPU, cache v b nh chnh.

CPU c/ghi cc phn t d liu n l vi cache. Cache c/ghi cc kh d liu ln vi b nh chnh.

Cu hi 1.13: Nu c im chnh ca a CD v a DVD. Cc a quang hot ng da trn nguyn l quang hc: a c ch to bng plastic; Mt mt a c trng mt lp nhm mng phn x tia laser; Mt a c khc rnh v mc lm ca rnh c s dng biu din cc bit thng tin; Cu hi 1.14: Nu nguyn l hot ng ca chut quang. Mt i-t pht nh sng qua ng knh chiu xung mt phng di chut; nh sng phn x t mt phng di chut quay ngc tr li chut; Mt camera t pha di chut lin tc chp nh ca b mt di chut nh nh sng phn x. Tc chp l khong 1500 nh/giy; IC iu khin chut s phn tch v so snh cc nh k nhau v qua pht hin ra chuyn ng chut; Tn hiu biu din chuyn ng chut do IC iu khin chut sinh ra c chuyn cho my tnh x l. Cu hi 2.1: Nu s khi chc nng v chc nng chnh ca cc thnh phn trong mt h thng my tnh ?

Cc thanh ghi (Registers) B nh trong (Internal Memory): Chc nng: lu tr lnh (instruction) v d liu (data) cho CPU x l; B nh trong bao gm: ROM (Read Only Memory): Lu tr lnh v d liu ca h thng Thng tin trong ROM vn tn ti khi mt ngun nui RAM (Random Access Memory) Lu tr lnh v d liu ca h thng v ngi dng Thng tin trong RAM s mt khi mt ngun nui Cc thit b vo ra (Peripheral devices) Thit b vo (Input devices): nhp d liu v iu khin Bn phm (Keyboard) Chut (Mice) a (Disk drives) My qut (Scanner) Cc thit b ra (Output devices): kt xut d liu Mn hnh (Monitor/screen) My in (Printer) My v (Plotter) a (Disk drives) Bus h thng (system bus): Bus h thng l mt tp cc ng dy kt ni CPU vi cc thnh phn khc ca my tnh Bus h thng thng gm: Bus a ch (Address bus) Bus A Bus d liu (Data bus) Bus D Bus iu khin (Control bus) - Bus C

Cu hi 2.2 : Nu s v cc c im ca kin trc my tnh von-Neumann. Kin trc my tnh von-Neumann hin i khc kin trc my tnh von-Neumann c in nhng im chnh no ?

Kin trc von-Neumann da trn 3 khi nim c s: Lnh v d liu c lu tr trong b nh c ghi chia s; B nh c nh a ch theo vng, khng ph thuc vo ni dung n lu tr; Cc lnh ca mt chng trnh c thc hin tun t. Cc lnh c thc hin theo 3 giai on (stages) chnh: CPU c (fetch) lnh t b nh; CPU gii m v thc hin lnh; nu lnh yu cu d liu, CPU c d liu t b nh; CPU ghi kt qu thc hin lnh vo b nh (nu c).

B x l trung tm (Central Processing Unit - CPU): Chc nng: c lnh t b nh Gii m v thc hin lnh CPU bao gm: B iu khin (Control Unit - CU) B tnh ton s hc v logic (Arithmetic and Logic Unit - ALU)

Cu hi 2.3 : Nu s v cc c im ca kin trc my tnh Harvard. Kin trc my tnh Harvard c nhng u im g so vi kin trc my tnh von-Neumann. Cc my tnh hin i ngy nay s dng kin trc no ?

Cu hi 2.4: Nu s khi tng qut v chu trnh x l lnh ca CPU.

Cu hi 2.5: Nu s khi v chc nng ca cc khi iu khin (CU) v khi tnh ton s hc v logic (ALU). n v iu khin CU

B nh c chia thnh 2 phn: B nh lu m chng trnh B nh lu d liu CPU s dng 2 h thng bus giao tip vi b nh: But a ch/ d liu cho b nh d liu But a ch/ d liu cho b nh chng trnh Nhanh hn nh but rng hn H tr cc truy nhp c/ ghi b nh ng thi, lm gim xung t. Kin trc Harvard nhanh hn kin trc vonNeumann do bng thng ca bus ln hn; H tr nhiu thao tc c/ghi b nh ti mt thi im gim xung t truy nhp b nh, c bit khi CPU s dng k thut ng ng (pipeline).

Chu trnh x l lnh ca CPU 1. Khi mt chng trnh c thc hin, h iu hnh (OS Operating System) np m chng trnh vo b nh trong; 2. a ch ca nh cha lnh u tin ca chng trnh c np vo b m chng trnh PC; 3. a ch nh cha lnh t PC c chuyn n bus A thng qua thanh ghi MAR; 4. Bus A chuyn a ch nh n n v qun l b nh (MMU - Memory Management Unit); 5. MMU chn ra nh v thc hin lnh c ni dung nh; 6. Lnh (cha trong nh) c chuyn ra bus D v tip theo c chuyn tip n thanh ghi MBR; 7. MBR chuyn lnh n thanh ghi lnh IR; IR chuyn lnh vo b iu khin CU; 8. CU gii m lnh v sinh cc tn hiu iu khin cn thit, yu cu cc b phn chc nng nh ALU thc hin lnh; 9. Gi tr a ch trong b m PC c tng ln 1 n v v n tr n a ch ca nh cha lnh tip theo; 10.Cc bc t 3-9 c lp li vi tt c cc lnh ca chng trnh.

n v iu khin CU (Control Unit) iu khin ton b cc hot ng ca CPU theo xung nhp ng h; CU nhn 3 tn hiu u vo: Lnh t IR Gi tr cc c trng thi Xung ng h CU sinh 2 nhm tn hiu u ra: Nhm tn hiu iu khin cc b phn bn trong CPU; Nhm tn hiu iu khin cc b phn bn ngoi CPU CU s dng nhp ng h ng b cc n v chc nng trong CPU v gia CPU vi cc b phn bn ngoi. n v s hc & logic ALU

ALU (Arithmetic and Logic Unit) bao gm mt lot cc n v chc nng con thc hin cc php ton s hc v logic: B cng (ADD), b tr (SUB), b nhn (MUL), b chia (DIV),.... Cc b dch (SHIFT) v quay (ROTATE) B ph nh (NOT), b v (AND), b hoc (OR) v b hoc loi tr (XOR) ALU c: 2 cng vo IN: nhn ton hng t cc thanh ghi; v 1 cng ra OUT: kt ni vi bus trong chuyn kt qu n thanh ghi.

Cu hi 2.6: Lnh my tnh l g ? Chu k lnh l g ? Nu cc pha in hnh trong chu k thc hin lnh. Nu dng lnh tng qut v cc thnh phn ca n. Lnh my tnh (computer instruction): L mt t nh phn (binary word); Mi lnh c gn mt nhim v c th; Lnh c lu tr trong b nh Lnh c c (fetch) t b nh vo CPU gii m v thc hin. Chu k thc hin lnh (Instruction execution cycle): l khong thi gian m CPU thc hin xong mt lnh: Mt chu k thc hin lnh c th gm mt s giai on thc hin lnh; Mt giai on thc hin lnh c th gm mt s chu k my; Mt chu k my c th gm mt s chu k ng h. Vic thc hin lnh c th c chia thnh cc pha (phase) hay giai on (stage). Mi lnh c th c thc hin theo 4 giai on: c lnh (Instruction fetch IF): lnh c c t b nh v CPU; Gii m (Instruction decode ID): CPU gii m lnh; Thc hin (Instruction execution EX): CPU thc hin lnh; Lu kt qu (Write back WB): kt qu thc hin lnh (nu c) c lu vo b nh.

Cu hi 2.7: Nu cc dng a ch ca lnh. Cho v d minh ho vi mi dng a ch. Ton hng 3 a ch: Dng: opcode addr1, addr2, addr3 Mi a ch addr1, addr2, addr3 tham chiu n mt nh hoc mt thanh ghi. V d: ADD R1, R2, R3; R1 R2 + R3 R2 cng vi R3, kt qu gn vo R1. Ri l thanh ghi ca CPU. ADD A, B, C; M[A] M[B] + M[C] A, B, C l a ch cc nh. Ton hng 2 a ch: Dng: opcode addr1, addr2 Mi a ch addr1, addr2 tham chiu n mt nh hoc mt thanh ghi. V d: ADD R1, R2; R1 = R1 + R2 R1 cng vi R2, kt qu gn vo R1. Ri l thanh ghi ca CPU. ADD A, B; M[A] M[B] + M[B] A, B l a ch cc nh. Ton hng 1 a ch: Dng: opcode addr1 a ch addr1 tham chiu n mt nh hoc mt thanh ghi. dng 1 a ch, thanh ghi Racc (Accumulator) c s dng nh a ch addr2 trong dng 2 a ch. V d: ADD R1; Racc = Racc + R1 R1 cng vi Racc, kt qu gn vo Racc. R1 l thanh ghi ca CPU. ADD A; Racc Racc + M[A] A l a ch mt nh. Ton hng 1,5 a ch: Dng: opcode addr1, addr2 Mt a ch tham chiu n mt nh v a ch cn li tham chiu n mt thanh ghi. Dng 1,5 a ch l dng hn hp gia nh v thanh ghi. V d: ADD A, R1; M[A] M[A] + R1 Ni dung nh A cng vi R1, kt qu lu vo nh A. R1 l thanh ghi ca CPU v A l a ch mt nh. Ton hng 0 a ch: c s dng trong cc lnh thao tc vi ngn xp: PUSH v POP.

Cu hi 2.8: C ch x l xen k dng lnh (ng lnh pipeline) l g ? Nu cc c im ca c ch ng lnh. C ch ng lnh (pipeline) hay cn gi l c ch thc hin xen k cc lnh ca chng trnh l mt phng php thc hin lnh tin tin, cho php ng thi thc hin nhiu lnh, gim thi gian trung bnh thc hin mi lnh v nh vy tng c hiu nng x l lnh ca CPU.

(a) Khng pipeline

(b) C pipeline Vic thc hin lnh c chia thnh mt s giai on v mi giai on c thc thi bi mt n v chc nng khc nhau ca CPU. Nh vy CPU c th tn dng ti a nng lc x l ca cc n v chc nng ca mnh, gim thi gian ch cho tng n v chc nng. c nhiu lnh ng thi c thc hin gi nhau trong CPU v hu ht cc n v chc nng ca CPU lin tc tham gia vo qu trnh x l lnh. S lng lnh c x l ng thi ng bng s giai on thc hin lnh.

Dng tng qut ca lnh gm 2 thnh phn chnh: M lnh (Opcode - operation code): mi lnh c m lnh ring a ch ca cc ton hng (Addresses of Operands): mi lnh c th gm mt hoc nhiu ton hng. C th c cc dng a ch ton hng sau: 3 a ch 2 a ch 1 a ch 1,5 a ch 0 a ch

Cu hi 2.9: Nu cu trc phn cp ca h thng b nh my tnh. Ti sao cu trc phn cp ca h thng b nh c th gip tng hiu nng v gim gi thnh sn xut my tnh ?

Dung ho c CPU c tc cao v phn b nh chnh v b nh ngoi c tc thp; Thi gian trung bnh CPU truy nhp d liu t h thng nh tim cn thi gian truy nhp cache. Gim gi thnh sn xut Cc thnh phn t tin (thanh ghi v cache) c s dng vi dung lng nh; Cc thnh phn r tin hn (b nh chnh v b nh ngoi) c s dng vi dung lng ln; tng gi thnh ca h thng nh theo m hnh phn cp s r hn so vi h thng nh khng phn cp c cng tc . Cu hi 2.10: Phn bit b nh RAM tnh v RAM ng. Ti sao b nh RAM ng cn qu trnh lm ti v RAM ng thng r hn RAM tnh ? RAM tnh (Static RAM SRAM): Mi bt SRAM da trn mt mch lt (flip-flop) Thng tin lu trong cc bit SRAM lun n nh v khng phi lm ti nh k SRAM nhanh hn nhng t hn DRAM. RAM ng (Dynamic RAM DRAM): Mi bt DRAM da trn mt t in Thng tin lu trong cc bit DRAM khng n nh v phi c lm ti nh k DRAM chm hn nhng r hn SRAM. RAM ng cn qu trnh lm ti v RAM ng thng r hn RAM tnh : Do t thng t phng in, in tch trong t c xu hng b tn hao theo thi gian. Cn np li thng tin trong t thng xuyn trnh mt thng tin. Vic np li thng tin cho t l qu trnh lm ti (refresh), phi theo nh k. DRAM thng r hn SRAM do: Cu trc n gin, dng t transitor Mt cy linh kin cao hn.

Cu hi 2.11: B nh cache l g ? Nu vai tr ca cache. Gii thch hai nguyn l hot ng ca cache. Cache l mt thnh phn trong h thng nh phn cp ca my tnh: Cache ng vai trong trung gian, trung chuyn d liu t b nh chnh v CPU v ngc li; Vai tr ca cache Tng hiu nng h thng Dung ho c CPU c tc cao v b nh chnh c tc thp; Thi gian trung bnh CPU truy nhp d liu t h thng nh tim cn thi gian truy nhp cache. Gim gi thnh sn xut Nu hai h thng nh c cng gi thnh, h thng nh c cache c tc truy nhp nhanh hn; Nu hai h thng nh c cng tc , h thng nh c cache c gi thnh r hn. Cc nguyn l hot ng ca cache Cache c coi l b nh thng minh: Cache c kh nng on trc yu cu v d liu v lnh ca CPU; D liu v lnh cn thit c chuyn trc t b nh chnh v cache CPU ch truy nhp cache gim thi gian truy nhp h thng nh. Cache hot ng da trn 2 nguyn l c bn: Nguyn l ln cn v khng gian (Spatial locality) Nguyn l ln cn v thi gian (Temporal locality) Nguyn l ln cn v khng gian: Nu mt nh ang c truy nhp th xc xut cc nh lin k vi n c truy nhp trong tng lai gn l rt cao; p dng: Ln cn v khng gian c p dng cho nhm lnh/d liu c tnh tun t cao trong khng gian chng trnh; Gii thch: Do cc lnh trong mt chng trnh thng tun t cache c c khi lnh t b nh chnh ph c cc nh ln cn ca nh ang c truy nhp. Nguyn l ln cn v thi gian: Nu mt nh ang c truy nhp th xc xut n

CPU registers (cc thanh ghi ca CPU): Dung lng rt nh, khong t vi chc bytes n vi KB Tc truy nhp rt cao (cc thanh ghi hot ng vi tc ca CPU); thi gian truy nhp khong 0,25ns Gi thnh t S dng lu ton hng u vo v kt qu ca cc lnh. Cache (b nh cache): Dung lng tng i nh (khong 64KB n 32MB) Tc truy nhp cao; thi gian truy nhp khong 1-5ns Gi thnh t Cn c gi l b nh thng minh (smart memory) S dng lu lnh v d liu cho CPU x l. Main memory (b nh chnh): Gm ROM v RAM, c kch thc kh ln; vi h thng 32 bt, dung lng khong 256MB-4GB Tc truy nhp chm; thi gian truy nhp khong 5070ns Gi thnh tng i r S dng lu lnh v d liu ca h thng v ca ngi dng. Secondary memory (b nh th cp b nh ngoi): C dung lng rt ln, khong t 20GB-1000GB Tc truy nhp rt chm; thi gian truy nhp khong 5ms Gi thnh r S dng lu d liu lu di di dng cc tp (files). Vai tro Tng hiu nng h thng

c truy nhp li trong tng lai gn l rt cao; p dng: Ln cn v thi gian c p dng cho d liu v nhm lnh trong vng lp; Gii thch: Cc phn t d liu thng c cp nht, sa i thng xuyn; Cache c c khi lnh t b nh chnh ph c c khi lnh ca vng lp. Cu hi 2.12: So snh cc chun ghp ni a cng IDE, SATA v SCSI. * Ging nhau : u l cc giao din ghp ni a cng vi my tnh * Khc nhau : IDE- SATA- SCSI -1. -ATA/IDE s dng cp dt 40 hoc 80 si ghp ni cng vi bng mch chnh; - SATA s dng cng tp lnh mc thp nh ATA nhng SATA s dng ng truyn tin ni tip tc cao qua 2 i dy; -SCSI l mt tp cc chun v kt ni vt l v truyn d liu gia my tnh v thit b ngoi vi; 2. - Mi cp thng h tr ghp ni vi 2 a -. - Tt c cc thit b SCSI u kt ni n bus SCSI theo cng mt kiu * u im : - - Truyn d liu nhanh v hiu qu Cm nng S dng t dy hn ATA truyn d liu. - SCSI cung cp tc truyn d liu v tnh n nh rt cao; Cm nng * Nhc im : - Tc truyn d liu cn chm -. - Cc cng SCSI thng rt t

Cu hi 2.13: Trnh by nguyn l c thng tin trn a CD.

Cu hi 2.15: Nu nguyn l to hnh nh ca mn hnh LCD. Cc tinh th lng khng th t pht sng: Chng c kh nng iu khin lng nh sng i qua theo nhit v dng in; C 2 loi LCD da trn phng php iu khin: LCD ma trn th ng (Passive matrix): + S dng li hoc ma trn nh ngha tng im nh (pixel) bi hng v ct ca n; + Mt im nh (giao gia 1 hng v 1 ct) c kch hot khi in p c t vo ct v dng tng ng c ni t. LCD ma trn ch ng (Active matrix): + S dng mt TFT (Thin Film Transistor) iu khin mt phn t LCD; + Cc TFT hot ng tng t nh cc b chuyn mch. TFT LCD l thit b c iu khin bng cc tn hiu in; Lp tinh th lng nm gia 2 lp trong sut cha cc in cc ITO (Indium Tin Oxide); Cc phn t tinh th lng c sp t theo cc hng khc nhau theo s thay i in p t vo cc in cc ITO; Hng ca cc phn t tinh th lng trc tip nh hng n cng nh sng i qua v n gin tip iu khin mc sng / ti (cn gi l mc xm) ca nh hin th; Mu ca hnh nh c to bi mt lp lc mu; Mc xm ca cc im nh c thit lp theo mc in p ca tn hiu video a vo.

Nguyn l c CD-ROM Tia laser t it pht laser i qua b tch tia n gng quay; Gng quay c iu khin bi tn hiu c, li tia laser n v tr cn c trn mt a; Tia phn x t mt a phn nh mc li lm trn mt a quay tr li gng quay; Gng quay chuyn tia phn x v b tch tia v sau n b cm bin quang in; B cm bin quang in chuyn i tia laser phn x thnh tn hiu in u ra. Cng ca tia laser c biu din thnh mc tn hiu ra. Cu hi 2.14: Nu nguyn l hot ng ca my in laser. My in laser hot ng da trn nguyn tc chp nh in t bng tia laser. C th: Trng cm quang c np mt lp in tch nh 1 in cc; Tia laser t ngun sng laser i qua mt gng quay v b iu ch tia c iu khin bi tn hiu cn in n mt trng; nh sng laser lm thay i mt in tch trn mt trng; Mt in tch trn mt trng thay i theo tn hiu cn in; Khi trng cm quang quay n hp mc th in tch trn trng ht cc ht mc c tch in tri du. Cc ht mc dnh trn trng biu din m bn ca vn bn/thng tin cn in; Giy t khay c ko ln cng c in cc np in tch tri du vi in tch ca mc nn ht cc ht mc khi trng cm quang. Giy tip tc i qua trng sy nng lm cc ht mc chy ra v b p cht vo giy.

Cu hi 3.1: Nu s v c im ca hai dng kin trc cache: Look Aside v Look Through. Trong hai dng kin trc trn, dng no c s dng nhiu hn trong thc t hin nay? Ti sao?

Cu hi 3.2 : So snh 3 phng php nh x cache: nh x trc tip, nh x kt hp y v nh x tp kt hp? Phng php nh x no trong cc phng php trn c s dng nhiu nht trong thc t? Ti sao? *Ging : -Cng l phng php nh x cache-mem -Cache c chia thnh cc dng *Khc nhau : nh x trc tipnh x kt hp y - nh x tp kt hp - B nh : m trang- 1 trang- m trang - nh x :

cache Look aside SRAM: RAM lu d liu cache Tag RAM: RAM lu a ch b nh Cache v b nh chnh cng kt ni vi bus h thng; Cache v b nh chnh thy chu k bus ca CPU ti cng mt thi im; u: Thit k n gin Miss nhanh Nhc: Hit chm

+nh x dng ca trang n dng ca ng (nh x c nh) + Mt dng trong b nh c th c nh x vo mt dng bt k trong cache; +nh x trang n ng (nh x mm do): Mt trang ca b nh c th nh x n mt ng bt k ca cache. nh x dng ca trang n dng ca ng (nh x c nh): * u : - Thit k n gin Nhanh do nh x l c nh: khi bit ch nh c th tm c v tr ca n trong cache rt nhanh chng. - Gim c xung t do nh x l khng c nh H s Hit cao hn nh x trc tip. - Nhanh do nh x trc tip c s dng cho nh x dng (chim s ln nh x); Gim xung t do nh x t cc trang b nh n cc ng cache l mm do. H s Hit cao hn. * Nhc : - Do nh x c nh nn d gy xung t H s hit khng cao. - Chm do cn phi tm a ch nh trong cache Phc tp do cn c n b so snh a ch b nh trong cache. Thng c s dng vi cache c dung lng nh. - Phc tp trong thit k v iu khin v cache c chia thnh mt s ng.

cache Look through Cache nm gia CPU v b nh chnh; Cache thy chu k bus ca CPU trc, sau n chuyn chu k bus cho b nh chnh; u: Hit nhanh Nhc: Thit k phc tp t tin Miss chm

Cu hi 3.3: Nu cc phng php c ghi v cc chnh sch thay th dng cache. Ti sao thay th dng cache s dng phng php LRU c kh nng cho h s on trng (hit) cao nht ? c thng tin: +Trng hp hit (mu tin cn c c trong cache) Mu tin c c t cache vo CPU; B nh chnh khng tham gia. +Trng hp miss (mu tin cn c khng c trong cache) Mu tin trc ht c c t b nh chnh vo cache; Sau n c chuyn t cache vo CPU. y l trng hp miss penalty: thi gian truy nhp mu tin bng tng thi gian truy nhp cache v b nh chnh. Ghi thng tin: +Trng hp hit (mu tin cn ghi c trong cache) Ghi thng (write through): mu tin c ghi ng thi ra cache v b nh chnh; Ghi tr (write back): mu tin trc ht c ghi ra cache v dng cha mu tin c ghi ra b nh chnh khi dng b thay th. +Trng hp miss (mu tin cn ghi khng c trong cache) Ghi c c li (write allocate / fetch on write): mu tin trc ht c ghi ra b nh chnh v sau dng cha mu tin c c vo cache; Ghi khng c li (write nonallocate): mu tin ch c ghi ra b nh chnh (dng cha mu tin khng c c vo cache). Chnh sch thay th (replacement policies) xc nh cc dng cache no c chn thay th bi cc dng khc t b nh. Cc chnh sch thay th: -Ngu nhin (Random) -Vo trc ra trc (FIFO) -Thay th cc dng t c s dng gn y nht (LRU). Thay th cc dng t c s dng gn y nht (LRULeast Recently Used): Cc dng cache t c s dng gn y nht c la chn thay th. u: C h s miss thp nht so vi thay th ngu nhin v thay th FIFO Do thay th LRU c xem xt n cc dng ang c s dng

Cu hi 3.4: RAID l g? Ti sao RAID c th nng cao c tnh tin cy v tc truy nhp h thng lu tr? Cu hnh RAID no ph hp hn vi my ch c s d liu trong ba loi RAID 0, RAID 1 v RAID 10? RAID (Redundant Array of Independent Disks) l mt cng ngh to cc thit b lu tr tin tin trn c s a cng, nhm t c cc mc ch: Tc cao (High performance / speed) Tnh tin cy cao (High reliability) Dung lng ln (Large volume) RAID: Mt mng ca cc a cng; Cc a cng theo chun SATA v SCSI mi h tr to RAID. Hai k thut chnh c s dng trong RAID: To lt a (Disk Stripping): Ghi: D liu c chia thnh cc khi, mi khi c ghi ng thi vo mt a c lp; c: Cc khi d liu c c ng thi cc a c lp, v c ghp li to d liu hon chnh. tc truy nhp c ci thin. Soi gng a (Disk Mirroring): Ghi: D liu c chia thnh cc khi, mi khi c ghi ng thi vo nhiu a c lp; Ti mi thi im ta lun c nhiu hn 1 bn sao vt l ca d liu. Tnh tin cy c ci thin. RAID 10

Cu hi 3.5: Nu cc c im chnh ca kin trc bus PCI v PCI-Express. Ti sao bus PCI-Express c kh nng h tr nhiu cp thit b truyn d liu ng thi vi tc cao? Bus PCI Express Kin trc PCI Express c cu trc t cc lin kt ni tip im n im; Mt cp lin kt ni tip (theo 2 chiu ngc nhau) to thnh mt lung (lane); Cc lung c nh tuyn qua mt b chuyn mch (crossbar switch) trn bng mch chnh; Cc khe cm PCI Express vt l c th cha t 1 n 32 ln. PCI Express s dng giao thc truyn ni tip v trnh c vn timing skew (lch thi gian) mt trong cc yu t lm gim tc : Cc loi bus song song (ISA, PCI, AGP) i hi tt c cc bit ca mt n v d liu phi n ch ti mt thi im; Do vn timing skew, cc bt ca mt n v d liu c th khng n ch ng thi gy kh khn cho vic khi phc n v d liu; Phng thc truyn ni tip khng gp phi vn timing skew do giao thc ny khng i hi tt c cc bit ca mt n v d liu phi n ch ti mt thi im.

Cu hi 3.8: Cho on chng trnh sau (R1, R2 l cc thanh ghi): 1.LOAD R2, #400 2. LOAD R1, #1200 3. STORE (R1), R2 4. SUBSTRACT R2, #20 5. ADD 1200, #10 6. ADD R2, (R1) a.Xc nh ch a ch v ngha ca tng lnh; b.Xc nh gi tr ca thanh ghi R2 sau khi thc hin xong lnh s (6). (1) Ch a ch tc thi. Lu gi tr 400 vo thanh ghi R2. R2=400 (2) Ch a ch tc thi Lu gi tr 1200 vo thanh ghi R1 R1=1200 (3) Ch a ch gin tip qua thanh ghi Lu gi tr ca thanh ghi R2 vo nh c a ch l gi tr ca thanh ghi R1 Tc l M[R1]=R2 hay M[1200]=400; (4) Ch a ch tc thi Tr gi tr ca thanh ghi R2 i 20 n v R2=R2-20= 400-20=380 (5) Ch a ch tc thi Cng them 10 n v vo gi tr nh 1200 M[1200]=M[1200]+10= 400 + 10 = 410 (6) Ch a ch gin tip qua thanh ghi Cng gi tr nh c a ch l gi tr ca thanh ghi R1 vo R2 Tc l R2= R2+M[R1] = 380 + 410 = 790 Cu hi 3.9: Cho on chng trnh sau (R1, R2 l cc thanh ghi): 1.LOAD R2, #500 2.LOAD R1, #2000 3.STORE (R1), R2 4.ADD 2000, #30 5.SUBSTRACT R2, #15 6.ADD R2, (R1) a.Xc nh ch a ch v ngha ca tng lnh; b.Xc nh gi tr ca thanh ghi R2 sau khi thc hin xong lnh s (6). (1) Ch a ch tc thi. Lu gi tr 500 vo thanh ghi R2. R2=500 (2) Ch a ch tc thi Lu gi tr 2000 vo thanh ghi R1 R1=2000

u im: An ton cao: do ti mi thi im RAID lun cha nhiu bn copy ca d liu cc a vt l khc nhau. Nhanh: tc truy nhp t l vi s a ca RAID

(3) Ch a ch gin tip qua thanh ghi Lu gi tr ca thanh ghi R2 vo nh c a ch l gi tr ca thanh ghi R1 Tc l M[R1]=R2 hay M[2000]=500; (4) Ch a ch tc thi Cng them 30 n v vo gi tr nh 2000 M[2000]=M[2000]+30= 500 + 30 = 530 (5) Ch a ch tc thi Tr gi tr ca thanh ghi R2 i 15 n v R2=R2-5= 500-15=485 (6) Ch a ch gin tip qua thanh ghi Cng gi tr nh c a ch l gi tr ca thanh ghi R1 vo R2 Tc l R2= R2+M[R1] = 485 + 530 = 1015 Cu 4 (3 im): Cho on chng trnh sau (R1, R2 l cc thanh ghi): (1) LOAD #1500, R1 (2) LOAD #300, R2 (3) STORE R2, (R1) (4) SUBSTRACT #5, R2 (5) ADD #10, 1500 (6) ADD (R1), R2 a. Xc nh ch a ch v ngha ca tng lnh; b. Xc nh gi tr ca thanh ghi R2 sau khi thc hin xong lnh s (6). Gii: (1) Ch a ch tc thi. Lu gi tr 1500 vo thanh ghi R1. R1=1500 (2) Ch a ch tc thi Lu gi tr 300 vo thanh ghi R2 R2=300 (3) Ch a ch gin tip qua thanh ghi Lu gi tr ca thanh ghi R2 vo nh c a ch l gi tr ca thanh ghi R1 Tc l M[R1]=R2 hay M[1500]=300; (4) Ch a ch tc thi Tr gi tr ca thanh ghi R2 i 5 n v R2=R2-5= 300-5=295 (5) Ch a ch tc thi Cng them 10 n v vo gi tr nh 1500 M[1500]=M[1500]+10= 300 + 10 = 310 (6) Ch a ch gin tip qua thanh ghi Cng gi tr nh c a ch l gi tr ca thanh ghi R1 vo R2 Tc l R2= R2+M[R1] = 295 + 310 = 605