.

model small
.stack 100h
.data
.code
;**************
mov ax,@data

mov ds,ax
+++
mov ah,4ch

int 21h
;**************
2
end

pseudoinstructions
KB 64 :

. .

Yehezkel .C

Program structure - MASM conventions

; This program file name.asm was written by .. Date ..
; It prints the following string 5 times
Five equ 5
assume cs:cod_seg, ds:dat_seg, ss:st_seg
dat_seg
segment
message
db 'Hello',13,10,'$'
dat_seg
ends
st_seg
segment
DW 10 dup(?)
st_seg
ends
cod_seg
segment

Program Image- Memory models

Wikipedia

start: mov ax,dat_seg

mov ds,ax
mov cx, Five
;Loop for 5 prints
again: mov ah,9h
mov dx,offset message
int 21h
loop again
mov ah,4ch
int 21h
cod_seg
ends
4
end
cs:start, ds:dat_seg, ss:st_seg

. .

. .

MASM conventions

Assembly in Linux and in DOS

Linux

DOS

; proc fileWrite - write proc fileWrite

mov ah,40h
a string to a file
fileWrite:
; write DOS service
mov eax,4
mov bx,[filehandle]
; write system call
; File handle
mov ebx,[filedesc]
mov cl,[stuffLen]
mov dx,offset
; File descriptor
mov ecx,stuffToWrite
stuffToWrite
mov edx,[stuffLen]
int 21h
int 80h
ret
ret
endp fileWrite
; endp fileWrite

assume cs:cod_seg, ds:dat_seg, ss:st_seg

dat_seg segment
message db 'Hello',13,10,'$'
dat_seg ends
st_seg segment
DW 10 dup(?)
stack_top label word
st_seg ends
cod_seg segment

. .

start: mov ax,dat_seg

mov ds,ax
mov ax,st_seg
mov ss,ax
mov sp, offset stack_top
mov ah,9h
mov dx,offset message
int 21h
mov ah,4ch
int 21h
cod_seg ends
6

. .

end cs:start, ds:dat_seg, ss:st_seg


.code, .data, .stack :

.data
:
.stack 100h
:
.code
:

#define C
:
zero equ 0

zero = 0
:
mov al, zero
??
8

. .

:
Data
.code Segment
db
: Byte
dw
: Word
dd : Word double
7

. .

" "

Editor

Assembler

Linker

ASCII

01010

File.asm

File.obj

CODE SEGMENT
ASSUME CS:CODE, DS:DATA
;
START: MOV AX,CODE
;
MOV DS,AX

Loader

01010110

01010110
File.exe

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

12

45

0000
0000
0000

CODE ENDS
END START

10

mov ax,0b800h
mov ds,ax

;intializing data segment

0005 BB 0000
0008 B0 41
000A
startlp1:
000A 88 07
000C 81 C3 00A0
0010 FE C0
0012 3C 60
0014 75 F4

mov bx,0h
mov al,41h

;intilizing location for display of 1st column

;the char A
;1st loop for displaying a column of capital letters
;displaying the current ascii
;move to the next line
;next char
;comparing to the char Z

0016 BB 0040
0019 B0 61
001B
startlp2:
001B 88 07
001D 81 C3 00A0
0021 FE C0
0023 3C 7A
0025 75 F4

mov bx,40h
mov al,61h

0027 BB 0080
002A B0 80
002C
startlp3:
002C 88 07
002E 81 C3 00A0
0032 FE C0
0034 3C 9A
0036 75 F4

mov bx,80h
mov al,80h

0038 B4 4C
003A CD 21

mov ah,4ch
int 21h

mov ds:[bx],al
add bx,160
inc al
cmp al,Z
jnz startlp1

;intilizing location for display of 3rd column

;the first hebrew char
;3rd loop for displaying the hebrew letters
;displaying the current ascii
;move to the next line
;next char
;comparing the last hebrew char

mov ds:[bx],al
add bx,160
inc al
cmp al,9ah
jnz startlp3

;interrupt - control restored to the os

. .end

Pseudocode / directives

:
. .

Intel/Microsoft tools:

;intilizing location for display of 2nd column

;the char a
;2nd loop for displaying a column of small letters
;displaying the current ascii
;move to the next line
;next char
;comparing to the char z

mov ds:[bx],al
add bx,160
inc al
cmp al,7ah
jnz startlp2

Intel/Microsoft tools
Unix tools

.model small
.stack 100h
.code

0000 B8 B800
0003 8E D8

2
10
11

comments

01010111

0101010111101110100
0101010111101110100
0101010111101110100

. .

Pseudocode / directives

01010110
11110110

10

12

- op dest, src
- implied width => requires adding BYTE PTR if not clear
- many other goodies (structures style)
MOV EAX, ECX
; EAX:=ECX
MOV BYTE PTR GS:[EAX]+4, 0 ; GS:[EAX+4]:=0
REP MOVSB
REP MOVS
BYTE PTR ES:[EDI], BYTE PTR DS:[ESI]
ADD BX,[EAX+EDX*2]+4
; 16 bit opsize
ADD EBX, [BX+SI]
; 16 bit addr
STRING:
DB
A,B,C, 0
Unix tools:
- op src, dest
- explicit width
- case sensitive
- less flexible
movl %ecx,%eax
movb 0, %gs:4(%eax)
rep movsb
addw 4(%eax,%edx,2),%bx
11 addl (%bx,%si),%ebx
. .
L001: .4byte abc,0

11

PORT_D = 61h
0000
10
0000

12

0104
0105

?Little Endian /Big Endian

0000

.data

14

0000 FFFF

TONE

17

0002 02FF

RATE DW

0004 0060
0006 0120

PERIOD DW
TONUM DW

18
21
22

DW

0FFFFH

24

34 LSB
12 MSB

0106

;counter value to specify

02FFH
60h
120h

;number of periods
:
;number of swept tones 23

;--------------------------------------------------- CODE SEGMENT

25

0008

27
28
30
32
33

0000
0003
0005
0005
0007

.code

B8 0000s
8E D8

MOV AX, @DATA

MOV DS, AX
MAIN PROC FAR
;MAIN procedure
IN AL, PORT_D ;read value from port
MOV AH, AL
;save value to AH

E4 61
8A E0

34

0009 8B 16 0002r

35

000D 24 FE

46
47
48
49
50

001C 8A C3
001E E6 61
0020 E8 0019

51

0025 E6 61

MOV
AND

L1:

0023 8A C4

DX, RATE
AL, 11111110B ;set xxxxxx10 to AL

MOV AL, BL
OUT 61H, AL
CALL DELAY

;set AL to
;spkr ON

ON value

MOV

;set AL to

OFF value

AL, AH

OUT

PORT_D, AL

0027 E8 0012

CALL

54

002A E2 F0

LOOP

55
69
70
71
72
74

002C
0041 E2 FE
0043 59
0044 C
0045

52

DELAY

53

0107
. .

;--------------------------------------------------- DATA SEGMENT

13

:
Offset = Value of label $ (offset of next instruction to be allocated)
:( )
.002C IP Loop L1
( Relative-Offset) loop
:
Offset= Value of label L1 - $(logic address of next Instruction)
=
1C2C
=
F0
a 100

0AF7:0100 dw A
0AF7:0102 dw 64
0AF7:0104 dw 1234
0AF7:0106 dw 2710
0AF7:0108
-u 100 108
0AF7:0100 0A00
0AF7:0102 64
0AF7:0103 0034
0AF7:0105 1210
0AF7:0107 27
140AF7:0108 0096F2AE

.model small
.stack 100h

11

14

13

L2:

LOOP

L2
POP
RET

;next period
;'do nothing' loop
;set counter to previous value

CX

. .DELAY

ENDP
;------------------------------------------- end of program

75

L1

13

END

Little Endian and Big Endian

DOUBLEWORD AT ADDRESS OAH
CONTAINS 12345678H

WORD AT ADDRESS 0BH

CONTAINS 3456H

.ASCII editor
BYTE AT ADDRESS 9
CONTAINS 9AH

compiler = assembler
.

WORD AT ADDRESS 6
CONTAINS DEF0H

0EH
12

0DH

34

0CH

56

0BH

78

0AH

9A

9H

BC

8H

DE

7H

F0

6H

QUADWORD AT ADDRESS 6
CONTAINS 123456789ABCDEF0H

5H

linker

4H
WORD AT ADDRESS 2
CONTAINS 74CBH
WORD AT ADDRESS 1
CONTAINS CB31H

16

3H

CB

2H

31

1H
0H

Loader -
.
. .

74

15

Bytes, word, double and quadrawords words

. .

15

High level Language

Assembly language

Machine Code
Microcode
18

. .

18

. .

17


microcode-
REG/OPCODE

MOD

R/M

SIB (SCALE INDEX BASE) BYTE

6 5
4
3 2
1

7
SS

INDEX

BASE

ModR/M and SIB byte Formats

Segment + Base + (Index * Scale) + Displacement

{}{}{}{} {
CS
SS
DS
ES
FS
GS

EAX
ECX
EDX
EBX
ESP
EBP
ESI
EDI

EAX
ECX
EDX
EBX
EBP
ESI
EDI

20

1
2

No Displacement
8-bit Displacement
32-bit Displacement

. .

20

RISC / CISC Variable length instructions!

Maximum 2 explicit operands - source and destination may be the same
Machine language
Zero or more prefixes
Opcode
Mod/Rm
Displacement
Immediate
8/16/32 Handling
Instruction encoding differs for 8-bit and 16/32 bit operands
Same instruction encoding is used for 16 and 32 bit operands
Current code segment defines if processor runs 16 or 32 bit code
In 16 bit code word operands indicate 16 bit operand,
In 32 bit code word operands indicate 32 bit operand.
19 This can be toggled by the operand-size
. .
prefix (0x66)

Instruction Format

MOD/RM-SIB

OPERAND- SEGMENT
INSTRUCTION ADDRESSPREFIX
SIZE PREFIX SIZE PREFIX OVERRIDE

16-bit addressing table

Table 11-1. 16-Bit Addressing Forms with the ModR/M Byte

AL
AX
EAX
0
000

Mod
00

01

10

11

R/M
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111

00
01
02
03
04
05
06
07
40
41
42
43
44
45
46
47
80
81
82
83
84
85
86
87
C0
C1
C2
C3
C4
C5
C6
C7

CL
CX
ECX
1
001

08
09
0A
0B
0C
0D
0E
0F
48
49
4A
4B
4C
4D
4E
4F
88
89
8A
8B
8C
8D
8E
8F
C8
C9
CA
CB
CC
CD
CE
CF

DL
DX
EDX
2
010

BL
BX
EBX
3
011

AH
SP
ESP
4
100

CH
BP 1
EBP
5
101

ModR/M Values in Hexadecimal

10
18
20
28
11
19
21
29
12
1A
22
2A
13
1B
23
2B
14
1C
24
2C
15
1D
25
2D
16
1E
26
2E
17
1F
27
2F
50
58
60
68
51
59
61
69
52
5A
62
6A
53
5B
63
6B
54
5C
64
6C
55
5D
65
6D
56
5E
66
6E
57
5F
67
6F
90
98
A0
A8
91
99
A1
A9
92
9A
A2
AA
93
9B
A3
AB
94
9C
A4
AC
95
9D
A5
AD
96
9E
A6
AE
97
9F
A7
AF
D0
D8
E0
E8
D1
D9
EQ
E9
D2
DA
E2
EA
D3
DB
E3
EB
D4
DC
E4
EC
D5
DD
E5
ED
D6
DE
E6
EE
D7
DF
E7
EF

DH
SI
ESI
6
110

30
31
32
33
34
35
36
37
70
71
72
73
74
75
76
77
B0
B1
B2
B3
B4
B5
B6
B7
F0
F1
F2
F3
F4
F5
F6
F7

0 OR 1

BH
DI
EDI
7
111

0 OR 1

REP
PREFIX

LOCK
PREFIX

0 OR 1

0 OR 1

0 OR 1

0 OR 1

NUMBER OF BYTES

38
39
3A
3B
3C
3D
3E
3F
78
79
7A
7B
7C
7D
7E
7F
B8
B9
BA
BB
BC
BD
BE
BF
F8
F9
FA
FB
FC
FD
FE
FF

OPCODE

MOD R/M

SIB

DISPLACMENT

IMMEDIATE

1 OR 2

0 OR 1

0 OR 1

0,1,2 OR 4

0,1,2 OR 4

NUMBER OF BYTES

Figure 25-1. Instruction Format

76543210

76543210

TTTTTTTT

TTTTTTTT

r8(/r)
r16(/r)
r32(/r)
/digit (Opcode)
REG =
Effective
Address
[BX+SI]
[BX+DI]
[BP+SI]
[BP+DI]
[SI]
[DI]
disp162
[BX]
[BX+SI]+disp83
[
BX+DI]+disp8
[BP+SI]+disp8
[BP+DI]+disp8
[SI]+disp8
[DI]+disp8
[BP]+disp8
[BX]+disp8
[BX+SI]+disp16
[BX+DI]+disp16
[BP+SI]+disp16
[BP+DI]+disp16
[SI]+disp16
[DI]+disp16
[BP]+disp16
[BX]+disp16
EAX/AX/AL
ECX/CX/CL
EDX/DX/DL
EBX/BX/BL
ESP/SP/AH
EBP/BP/CH
ESI/SI/DH
EDI/DI/BH

19

opcode
(one or two bytes)
(T represents an
opcode bit.)

Notes

7-6

5-3 2-0 7-6 5-3

2-0

mod TTT r/m ss index base d32|16|8| none

mod r/m
byte

s-i-b
byte

register and address

mode specifier

d32|16|8|none

address
displacement
(4, 2, 1 bytes
or none)

immediate
data
(4, 2, 1 bytes
or none)

MODR/M BYTE
4
3 2

{
{

6 5

1. The default segment register is SS for the effective addresses containing a BP index, DS for other effective addresses.
2. The disp16 nomenclature denotes a 16-bit displacement following the ModR/M byte, to be added to the index.

21

3.
The disp8 nomenclature denotes an 8-bit displacement following the ModR/M byte, to be signextended and added to the index.

Core Instruction Format

. .

, ,

Structure programming



,

piano[si]

............. , , , , , ,
24

. .

21

24

MS/Intel

programming tool

Case insensitive
Operand size implicit
Destination on left
Unix

compiler back-end

Case sensitive
Operand size explicit
Destination on right
Assembler should be smart enough to handle prefix when 16 bit
operand is used in 32 bit code...
23

. .

23

Shift and Rotate

Shifting left one position means take one bit at the left,
then shift the remaining bits, then add one 0 at the end
Shl x,y ; x is shift left by y positions
Shr x,y ; x is shift right by y positions
The x and y usage is just like add or sub, you can have
registers, variables or constants. Of course the x part
cannot be a constant
What happened to the missing bits that get shifted out?
The carry flag will hold the last shifted-out bit

. .

27

26

-Bit Rolling

. .

26

SAL & SAR

rcl and rcr

. .

29

String
operations
There are 5 basic string instructions:
1. LES, LDS
2. MOVS
3. CMPS
4. SCAS
5. STOS , LODS
These instructions can be "emulated with
mov, cmp, loop and jmp. However, these
five brothers are a lot
34
. . faster since they are 34
"built-in" instructions

MUL - Unsigned Integer Multiply

IMUL - Signed Integer Multiply
MUL/IMUL r/m
MUL performs unsigned integer multiplication, and IMUL
perform signed integer multiplication..
The other operand to the multiplication, and the destination
operand are implicit, in the following way:
For MUL r/m8, AL is multiplied by the given operand. the
product is stored in AX.
For MUL r/m16, AX is multiplied by the given operand.
The product is stored in DX:AX.
For MUL r/m32, EAX is multiplied by the given operand.
The product is stored in EDX:EAX.
33

. .

33