21.10.

12 -1

VHDL
"
/http://www.abramovbenjamin.net :
.BVHDL :
/http://www.altera.com :
.Quartus II Subscription Edition Software Version 12.0 Service Pack 2 for Windows :
modelsim : .
biu.vhdl@gmail.com :
- VHDL - .
.

|1

VHDL

 31.10.12 2
:
(Programmable Logic Device) PLD .PAL , PLA , GAL PLD :
.
.CPLD ( ).
FF - AND .OR-
. .FPGA-"-" FPGA-,Xilinx (60%) :
) Altera (35%.)5%( Others -

:FPGA
.)In/out Bit( IOB/IOE
( FF ).
.(Global Interconnect) GI
.
GI- ) LA (Logic Array )Block( LAB LI
(Logic Element) LE- . LE FG -.FF-

FPGA .
) SoC (System on Chip FPGA .
(" .)4kb ( - SRAM )
." - ROM , RAM , FIFO , LIFO'.
) SoPC (System on Programmable Chip .
. :
* Hardcore ( ) .
* Softcore
. 16 .
( ) .DSP
( DSP)
( ).
( 78 .)!!!800Mb/s
PLL .DCM (Digital Clock Manager)-
.

|1

VHDL

 31.10.12 2
.12

:
23
24
25
27
28
29
30
31
32
36-37
38-39
40

46

|2

:
.HDL .
HDL Adder . .
( . )A-
C ( ) . HDL- D-
( ) .
.HDL-
Der der DER :.

-- :
.
.
.
.
)* .(Modes .
.
. .
inout Buffer-
. inout *** . ***inout
.(Types) . / .0/1
. . integer .

VHDL

 7.11.12 3
:
).(Modes
) (Type .
:
Shift

Relation
V
V
V
V
V
V

logical
V
V
V
V
V

Arithmetic

V
V
V

Type \ Operation
Boolian
bit
bit_vector
integer
std_logic
std_logic_vector

boolian bit- " . 'true','false' : '0','1'-.

integer bus- 32.
std_logic ( ) .std_logic_vector-
: , , .
: , , , , , , -.
.rem , mod , abs , ** , / , * , - , + :
, .
. .int-
( 2**m : ) ( m**2 -) . .
.
mod rem- . a mod b : a b
rem . , ,2 .x mod n :
not , or , and , nor , nand , xor , xnor : .
x s1 or s2 or s3 or s4 : .
. x s1 or s2 or s3 or s4 :
,2 .
.<= , >= , < , > , /= , = : : ,- , , , , .
boolian d s1 op s2 : d s2 , s1-
( int ).
( sll : )( sla , MSB ).
( srl ) " .sra :( rol : ) ( ror ).
s a sll b : b int .

|1

VHDL

 7.11.12 3
:
m n- MSB- .LSB-
, , . n- .

;)a: in bit_vector (m down to n

a: bit_vector 1 to 8 ; : MSB- (. )1
b: bit_vector 9 dwon to 2 ; :. c: bit_vector 7 dwon to 0 ; -
c a; :. c 7 =a 1 :
c a and c; :. b 8 a 2 and c 6 ; , b 9 a 1 and c 7 ; :
" .
.. a 2 to 4 b 8 down to 6 xor c 2 down to 0 :
, down to- .

:
.
bit .'1' , '0' : / . int .10
base#const# : - 16#ABCD# : ABCD .16
"" 5 ,9'...
bit_vector ) (string
. "0100111100" : " . b"0100111100" :
. . x O"1234567"; :. x X"1AFC"; :
3 4 .
. "01001000" "0100_1000" : .

; . a,b,c,d: bit e: bit_vector 3 down ot 0 ; : a,b,c,d .e

. e 3 a; e 2 b; e 1 c; e 0 d; : ( e a,b,c,d ; : ).
. . e a,"0",c,"1" ; :
. e 17 a,22 b,16 down to 9 "1",2:1:23:8 c , others d ; : .
:

; e: bit_vector 7 down ot 0
;"e "1" & b & 8 & O"6" & a & d & "0
e .

|2

VHDL

 14.11.12 4

Std_Logic ::Std_logic_vec-

.
inout 3 ) (3 state buffer Transmission gate .
1 , 0 .High-Z
9 :std_logic
-U .
X 0 1- .
0,1 .
W .
L,H / .
' '- ( .dont care ) . "
.
dont care- bus .
.disable
dont care .

' 'X' , '0' , '1' , 'Z .

:'X'-
If(S/=R) than
q R,
elseif (S='0') than
;'q 'X
;endif
.
elseif - . SR-FF ''00
. ' 'X -- . ' S='0' && R='0
elseif if()- .
' 'Z .

ENB

i3

ENB

Dout

i2
Decoder

ENB

i1
ENB

|1

:
.1000 , 0100 , 0010 , 0001

. ,
1
.High-Z

i0

VHDL

 14.11.12 4
:std_logic-
;Library IEEE
;Use IEEE.std_logic_1164.all
.
.use IEEE.std_logic_arith.all :
sign unsign use IEEE.std_logic_unsigned.all :
.use IEEE.stdlogic_signed.all if(c>x"04") than : " c=X"80
" . .
.
" :
;Library IEEE
;use IEEE.std_logic_1164.all
;use IEEE.std_logic_arith.all
;use IEEE.std_logic_unsigned.all

:Test-Bench (TB) -
.
UUT , DUT MUT .TB-
entity- TB- DUT-.component -
component-" ) (TG Test generator .
' 'U.
.signal s: type:=init_value; :
Begin DUT-.Port map-
. .clk not clk after 5ns; :
after . " .fs-
) (Continuous assignment .
.s1 '0', '1' after 10ns , '0' sfter 20ns , . :
.

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VHDL

 21.11.12 5

:Process-
VHDL process .
:
E1: process ( ) is
begin
;end process E1
E1 ( ) ) (sensitivity list
. . .
, .
" " .
. process
.
process :
(-) . () . .
. FF
.

:
Set.Reset (clr)-

SET

in1

in2
clk

CLR

FF - .reset set- reset-

set- .
;s a and b
:
;s a or b
decoder din , dout din .
dout others '0' ; : . dout conv_integer din '1'; :

, , .

. dout - 00000000 :
, ,3 .00001000 -

|1

VHDL

 21.11.12 5
Xor :

E1: process a, b, c is
begin
;s1 a xor b
;s 2 s1 xor c
;end process E1

" , , .s1
( " " ).
Process .
:

E1: process a is
begin
;s a xor b
;end process E1

b . .
b . a Xor- b .
Latch- enb- " a :
a

SET

CLR

SET

CLR

( Xor 16 16) Lacth 4 .

8 .

|2

VHDL

21.11.12 5

E1: process clk , arst is

begin
if then

elseif

: if
: enb FF

then

else
end if;
end process E1;
E1: process clk , arst is
begin
if arst '0 ' then

: enb FF

q '0 ';
elseif clk' event and clk 1'1 then
q d;
end if;
end process E1;

. elseif rising_edge clk then

. FF-
:T-FF

E1: process clk , arst is

begin
if arst '0 ' then

q '0 ';
elseif rising_edge clk then
if t '1' then
q not q;
end if;
end if;
end process E1;
.

VHDL

|3

21.11.12 5
:JK-FF-

E1: process clk , arst is

begin
if arst '0 ' then

q '0 ';
elseif rising_edge clk then
if J / k then
q J;
elseif J '1' then
q not q;
end if;
end if;
end process E1;
:) reset- ( reset FF-
.) :(
E1: process clk is
begin
if rising_edge clk then

SET

clk

if srst '0 ' then

CLR

q '0 ';
else q d;
end if;
end if;
end process E1;

reset

reset-


.
.

VHDL

|4

28.11.12 6

:Process
:Mux

E1: process x, y is
begin
if a b then

s x;
else s y;
end if;
end process E1;

Multiplexer

S1

S2

ENB

a=b

. a b : select mux
: .Latch " "
Multiplexer

S1

SET

CLR

S2
Q

ENB

y
D

SET

CLR

SET

CLR

SET

CLR

.)select MUX- ENB ( "

VHDL

|1

 28.11.12 6
process:

E1: process clk , rst , ld , adat is

begin
if rst '0 ' then
; s others '0 '
elseif rising_edge clk then
;s din
elseif ld '1' then
; s adat
;end if
;end process E1

" . elseif-
- . Q- , - ( set )reset- ().
. . .
.
:

E1: process clk , rst , data is

begin
if rst '0 ' then

;s data
elseif rising_edge clk then
;s din
;end if
;end process E1
. .Q
? " ..

)Data(4

reset

|2

VHDL

28.11.12 6
: , , reset ,11
E1: process clk , rst is
begin
if rst '0 ' then

count others '0 ' then

elseif rising_edge clk then

din
Add/
sub
Up/
down

Multiplexer
S1

S2

1
0
enb

ENB

count

load
rst

if load '1' then

count din;
elseif rising_edge enb '1' then
if up _ ndwn '1' then
count count 1;
else
count count 1;
end if;
end process E1;

E1: process clk , rst is

begin
if rst '0 ' then

:) (

q1 '0 ';
elseif rising_edge clk then
q1 d1;
q 2 d 2;
end if;
end process E1;
.reset- q2 q1 . ,FF 2
.)(
1 reset reset . reset q2- FF
: process .) (
E1: process clk is
begin
if rising_edge clk then

q 2 d 2;
end if;
end process E1;
-

d2

0
1

q2

rst

VHDL

|3

 28.11.12 6
:FF

E1: process clk is

begin
if rising_edge clk then

if srst '1' then

;' q1 '0
;else q1 d1
;q 2 q1
;end if
;end if
;end process E1
:
q2

q1
Q

SET

CLR

SET

din
srst

CLR

clk

q2- .reset- reset .1

:
d2
Q

SET

CLR

0
1
srst

SET

din
srst

CLR

clk

. ; q2 q1 . .

:
( ) . ( ) .
() .FF-

|4

VHDL

 5.12.12 7

:
).(process
if :
case sig is
;when "001" .........
;when "010" .........
;when "001" c1|c2|c3|c4|c5 .........
;when 1 to 11 .........
;when 11 downto 1 .........
;when others .........
;end case
. .
. s1 a b; :

:
; s2 .........
; s2 .........
; s2 .........
; s2 .........

case s1 is
"when "00
"when "01
"when "10
"when "11
;end case

std_logic 9 11.
;when others s2 .........
77 :
. ( )mux
s 2 y; : . when "11" s 2 y; :
:
case s1 is
;when "00" s2 .........
;when "01" s2 .........
;when "10" s2 .........
;when others s 2 y
;end case
NULL :
;when others NULL

NULL- - .
|1

VHDL

 5.12.12 7

:
.
3 .
:for
for i in n to m loop
)( m downto n
;end loop
, .
. m n :
next : exit- count-time- break-.
next . exit end loop .
( ) L1: for in n to m loop : .
:
L1: for . . . . loop
L2: for . . .
L3: for . . .
;End loop L3
;End loop L2
;End loop L1
next exit- .
:
.1 " .
. 2 .
:priority encoder

E1: process din is

begin
; dout others '0 '
for i in din'renge loop
; dout i din i
; exit when din i '1'
;end loop
;end process E1

|2

VHDL

5.12.12 7
:
. s s'renge
.s s'reverserenge
.s s'length
. s'low
. s'high
. s'left
. " s'right

signal s : stdlogic_vector 15 downto 0 ;

:shift left register

E1: process clk , rst is

begin
if rst '0 ' then
s others '0 ' ;
elseif rising_edge clk then
if enb '1' then
for i in s'reverserenge loop
if i s 'low then
s i sin;
else s i s i 1 ;
end if;
end loop;
end if;
end if;
end process E1;

:
s s s'high-1 downto s'low & sin ;

VHDL

|3

12.12.12 8
: "
int (!) 8
9 std_logic- .boolian
. s to_01ZX s1 ; : to_01ZX , to_01Z , to_01 :
.to S std_logic S1
.

:Generic Constant
:
entity e_name is
generic ( cont1: type:= init_value ; const2: type := init_value; . . . )
port (
);
end entity e_name;
:
entity gcnt is
generic (side : integer : = 100 )
port (
clk : in std_logic ;
rst : in std_logic ;
din : in std_logic_vector ((size-1) downto 0 ) ;
ld : in std_logic ;
en : in std_logic ;
dout : in std_logic ((size-1) downto 0 )
);
end entity gcnt;
architecture arc_ gcnt of gcnt is
signal out: std_logic_vector (dout'range);
begin
process (clk , rst) is
begin
if (rst = '0') then
out (others '0');
elseif rising_edge (clk) then
if (ld = '1') then
out din;
elseif (en ='1') then
out af+1;
end if;
end if;
end process;
dout count;
end architecture;
-

VHDL

|1

12.12.12 8
Port map - . Generic-
.

:Generate
. component
.component n . 2 Adder n adder
Carry_out- Carry_in ,carry_in , 3
: .n+1- Carry_out :
g1: for i in a'reverse_range generate
g2: if (i=a'low) ganarate
u1: fa
port map ( a a(i) ,
b b(i)
ci '0',
s s(i),
co c(i)
);
end_ganarate g2;
g3: if (i=a'high) generate
u1 : fa
port map
( a a(i) ,
b b(i) ,
ci c(i-1) ,
s s(i) ,
co s(i+1)
);
end_ganarate g3;
g4: if (i/= a'low and i/= a'high) generate
u1 : fa
port map
( a a(i) ,
b b(i) ,
ci c(i-1) ,
s s(i) ,
co c(i)
);
end_ganarate g4;
end_ganarate g1;

VHDL

|2

 12.12.12 8
. ,Carry - 11-
11 " ( :)Generate g1
;'c(0) '0
;)s(16) c(16
port map-.

generic- :
,s .Register :

"generic ( kind_of_output: string:= "registered"); -- "unregistered

) "g1: if (kind_of_output ="unregistered
;dout s
;end generate g1
g2: if (kind_of_output ="registered" ) generate
process (din) is
begin
if rising_edge (clk) then
;dout s
;end if
;end process
;end generate g2

:Wait Statement
wait- . . 4 :
- wait; .1 . .
- wait for time units; .2 , time- units- .
wait on s1,s2,.,sn; .3 .
wait until (cond.); .4 .
wait- "-" .
VHDL- time .signal t : time; :
Now . ( .t1 now; : t1 .)time
. if (now_t1) > 100 ns then :
.wait on rst until rising_edge(clk) for 1 us; : reset-
,1us .

|3

VHDL

 19.11.11 9

:
.
) (Hardware " ).(Software
.Operational Unit- " " " .Control Unit-
OU- Control-
( .)Status ) (Software external control
.external status
din

Data
Path
)(OU

control

ext.cntrl.

FSM
)(CU

status

microC/
user etc.

ext.statu
s.

dout

) (mealy .moore
:
( .)Mealy-

next state

in

out

next
state
logic

current
state

state
Reg.x

output
logic

moore- , . mealy- .
mealy- , ,
. .
VHDL- ( ") . :

_write
mem

y2

y2

x1

y1

idle

x1 x2

y1
x1

y1 y2

x1 x2

_read
mem

y2
x2

entity- type type fsm_st is ( ) :

.)idle , read mem , write mem) : .signal ns , cs : fsm_st ; :
.
. state Reg- . NS- ."
.Output- -latch.
. .
|1

VHDL

19.11.11 9
type fsm_st is (idle , read mem, write mem);
signal ns , cs : fsm_st;
begin
state_reg : process (clk , rst) is
begin
if (rst <= '0') then
cs <= idle;
elseif rising_edge (clk) then
cs<=ns;
endif;
end process state_reg;
common_logic: process (cs , x) is
--
begin
ns<=cs; --
y[2]<= '0' ;
y[1]<='0';
case cs is
when idle => if ( x[1]='1') then
ns <=read_mem;
y[2] <='1';
elseif ns<=idle;
y[1]<='1';
endif;
when read_mem => if (x[2]='1') then
ns <=write_mem;
y<='11';
elseif (x[1] = '0') then
ns<=idle;
y[1]<='1';
else ns<=read_mem;
y[2]<='1';
endif;
when write_mem => ns<=idle;
y[2]<='1';
end case;
end process;

VHDL

|2