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13.31.3. :

3-Bus SRC Processor Design :8

:
.3 SRC 3-BUS
RTN ..
.1
.4 ,Abstract RTN
: .
:3-bus

* : ( ) .
.

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.

. ,
( ) ( ) clock period
/ .
SRC concrete RTN
. , Trade-off (
) , .clock

:3-bus
3 ALU
.-Bus .ALU
fetch ..
:Memory interface fetch .
.MA MA ( cycle cycle
MA" .)edge-triggered ff
Read,Wait MABin
( clock cycle) .
MA cycle
( latch .).
:3 port register file 3-bus register file
. register file -port port
.
: register file
GAra, GArb, GArc, RAout : GBra, GBrb, GBrc, RBout
: 2-bus
BAout ( Port B decoder )bus B
( port A decoder )bus A BAoutbBAouta
.
MACin,MABin .MA
Goto5 .Goto6
C,A .
C B

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:3-Bus
:fetch fetch 2-bus fetch .3-bus

PCout,C=B,Main

Concrete RTN

;MA PC

2-Bus:
Step
T0

PCout,INC4,PCin,Read,Wait

;PC PC 4 : MD M MA

T1

MDout,C=B,IRin

;IR MD

T2

PCout,MABin,INC4,PCin,Read,
Wait
MDout,C=B,IRin

Concrete RTN
;MA PC : MD M [MA]: PC PC 4

;IR MD

3-Bus:
Step
T0

T1

: add

Step
T0 T1

Concrete RTN
fetch
;] R[ra ] R[rb ] R[rc

GArb, RAout, GBrc, RBout,ADD,

Sra,Rin,End

T2

1 ( 6.)1-bus

: ld

Concrete RTN
Fetch
GArb, BAout,c2out,ADD,
MACin,Read,Wait.
MDout,C=B,Sra,Rin,End

Step
T0 T1

)] MA ((rb 0) 0 : (rb 0) R[rb

T2

(16@ IR 16 # IR 15..0 ) :
;]MD M [ MA
;R[ra ] MD

T3

BUS ] R[rb ( 1 ,rb )

BUS ( c2 ) ALU .MA
MA ff latch T2
.
4 / .

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:1bus

Step
T0 T2

Concrete RTN
Fetch
BAout,Ain,Grb

(rb 0) ( A 0) :

C2out,ADD,Cin

;)] (rb 0) ( A R[rb

;}C A c2{sign Ext

T4

MAin,Cout

;MA C

T5

Read,Wait

;]MD M [MA

T6

MDout, Gra,Rin,End

;R[ra ] MD

T7

T3

( 1 )4
( 5.)6
3bus 4 ( 8.)1-bus

:1.8
mult ,2-bus
3-bus .
* .C=A
Mult ra , rb , rc :

0 R rc 31

Abstract RTN : R ra R rb R rc

:
:3-bus SRC

Concrete RTN
MA PC : MD M MA : PC PC 4; PCout,MABin,INC4,
PCin,Read,Wait.
;IR MD
MDout,C=B,IRin

GBrc,RBout, Ld, GArc,

BAouta,A=C,Sra,Rin,goto5
n 0 (GAra ,RAout, GBrb,
RBout, Add ,Sra, Rin ,Decr
),Goto5
n 0 End

;n R rc : R ra 0

: n 0 R ra R ra R rb
mult
;
:
n

;1
mult

Step
T0

T1

T2
T5

* ,T5-
-clock Goto5
( T2- T4,T3 ).

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:2-bus

:2-bus SRC
Step
T0

MA PC;

PCout,C=B,Main

Concrete RTN

T1

PC PC 4 : MD M MA;

PCout,INC4,PCin,Read,Wait

T2

IR MD;

MDout,C=B,IRin

n R rc ;

Grc,Rout,ld

T3
T4

A R rb ;

Grb,Rout, C=B ,Ain

T5

R ra 0;

BAout,C=B,Sra,Rin

: n 0 R ra R ra A
mult
;
:
n

1;
mult

Gra, Rout , ADD, Sra,

n 0

Rin , Decr , Goto6

n 0 End

T6

Execution Time=Clock Count

. RTN / -Clock :Clock Count
.)clock period( :
. 1.5 2bus 3bus , 2bus

5+(R[rc]+3( :3-bus ,6+(R[rc]+3( :2-bus :IC

:

Speedup

T2bus T3bus
(6 ( R[rc ] 1)) (5 ( R[rc ] 1))1.5
100
100
T3bus
(5 ( R[rc ] 1))1.5

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1.8
.Clroddbit
,Clroddbit ra, rb :
rb .ra
. RTN +
. RTN +
.

?Speed-Up

T2-BUS=1.15 ,T1-BUS=

: C2 Shift Control
C2 36
) RTN- clroddbit 1-Bus :

Concrete RTN

Step

Fetch

T0-T2

C 2out , Ld

;n IR 4..0

T3

Grb , Rout , Cin

;] C R[rb

T4

Cout , Gra , Rin

;R[ra ] C

T5

BAout , Not , Cin

;C 1

T6

Cout , Shl , Cin

;C C 30..0 #0

T7

Cout , Ain

;A C

T8

Gra , Rout , shc, Cin

;C R[ra ] 30..0 # R[ra ] 31

T9

Cout , And , Cin

;C A and C

T10

Cout , shc, Cin

;C C 30..0 # C 31

T11

;)R[ra ] C : n 0 (n n 1

T12

) (Cout , Gra , Rin

)n 0 ( Dec, goto6
n 0 End

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: 2-Bus clroddbit RTN-

Step

Concrete RTN

T0-T2

fetch

T3

n IR 4..0

C 2out , Ld

T4

R[ra ] R[rb ]

Grb , Rout , C B ,
, Sra , Rin , goto6

T6

R[rb ] 1

BAout , Not , Srb , Rin

T7

R[rb ] R[rb ] 30..0 #0

Grb , Rout , shl ,

, Sra , Rin

T8

A R[ra ] 30..0 # R[ra ] 31

Gra , Rout , shc, Ain

T9

R[ra ] A and R[rb ]

Grb , Rout , shc, Sra , Rin

R[ra ] R[ra ] 30..0 # R[ra ] 31 :

Gra , Rout , shc, Sra , Rin

T10

n 0 (n n 1)

n 0 ( Dec, goto6)
n 0 End

5- 2 Bus- . 7- 1 Bus-
. 36 .

% speed - up

To l d - Tn e w
Tn e w

100

(16 7 6 1) - (16 5 5 1) 1.15

(16 5 5 1) 1.15

100

119 98.9
98.9

100 20%

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1.3

( ) ,

SRC- rotate ra,rb,rc

:

]R[rb

]R[rc

]R[ra

ra ,- 3 R[ra] 111111....111

) ( 1) RTN-
) ( 31) RTN ( )fetch-
1-BUS .
) ( 5) ,
,Cout, Gra :
.
) ( 7) , ,
RTN .
) ( 5)
SpeedUp-

.
.

' .
:1-bus
ra -3 NOT .

Concrete RTN

fetch

Step
T0 T2

Gra,Rout,Ain,NOT,Cin

;] C R ra : A R[ra

T3

Cout,Conin

;) CON Cond (C

T4

CON Grc, Rout , C B, Cin

;] CON C R[rc

T5

CON End
Gra, Rout , ADD, Cin ,
n 0

Decr , Goto6

;R ra C

T6

; C R rb

T7

Cout,Rin,Grc

;R rc C

T8

BAout,ADD,Cin

;C A

Cout,Rin,Grb,End

;R rb C

T9

Cout , Gra, Rin , End

* : fetch .

T10

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:
opcode .7 . 1 LSB
( 010 .)type 3
3 bit
Cond=0102
.

unused

5 bit
rb

5 bit
rc

5 bit
ra

5 bit
Opcode=7

: "
.

,Cout, Gra :
:
) Cout (opcode 7)(T1 T4 T6 T8 T10
) Gra (opcode 7)(T3 T6

:
ra .-3
: 6 7
331.

3 bit
Cond=1102

unused

5 bit
rb

5 bit
rc

5 bit
ra

5 bit
Opcode=7
Step
T0 T2

Concrete RTN

fetch
Cout,Conin

;] CON Cond ( R[ra ]) : A R[ra

T3

CON Grc, Rout , C B, Cin

;] CON C R[rc

T4

CON End
Gra, Rout , ADD, Cin ,
n 0

Decr , Goto6

;R ra C

T5

; C R rb

T6

Cout,Rin,Grc

;R rc C

T7

BAout,ADD,Cin

;C A

Cout,Rin,Grb,End

;R rb C

T8

Cout , Gra, Rin , End

T9

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Told Tnew
11T 10T
100
100 10% : Speedup
Tnew
10T

1.4

Speedup

( ) ,

SRC- gray rb,rc rc

gray rb rc .
:

R[rc] .....0011010101101
R[rb] .....0101111110111
ALU- XOR XOR .ALU-
.

( .) RTN-

31( .) RTN ( )fetch-

1-BUS .
.

( 5) ,
,Cout, Grc : .

5( .) .2-BUS
1( .) 2 BUS 1.15 1 BUS -
.SpeedUp

:
8 . ;8 .
- 8 ,0 ( 8 .)XOR
800880 :

11
8,0 - 8
110
0,0 - 0
0,8 - 1101 8
8,8 - 11010 0
8,0- 110101 8
1

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SRC
1.5

( )

SRC- Grc "3"- .

( ? sub r2,r17,r5 : RTN)
R7 R21 R5

1.6

( )

SRC- . n
( 3- .)3-
data path-
. ,OR ,AND NOT- . .

1.7

( )

SRC MA BUS- , MD-

BUS . ,EXECUTE-
st r5, 24(r7) : ?
r5 ].24+R[7