Stack

:
.


-.

KB64.

LIFO - LAST IN FIRST OUT

.

Stack structure and

Subroutine
-

C. Yehezkel

SP . 2
SP
[SP-1]<= CL
[SP-2]<= CH
SP <= SP-2

SP -
, SP
. 2-
SP <= SP+2

:

:
>, PUSH AX < PUSH

:
> , POP AX < POP

C. Yehezkel

PUSH & POP

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PUSH CX

POP CX

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1000h

0FFFh

PUSH
POP

0FFEh

SP1

0FFDh

mov sp,1000H

0FFCh

PUSH CX
PUSH BX
POP BX
POP CX

0FFBh

C. Yehezkel

CH | CL

CX

BH | BL

BX

0FFAh
0FF9h
5

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PUSH BX

PUSH CX
SP1

CX

CH | CL

BX

BH | BL

SP2

SP3

SP1

1000h
0FFFh

CL

0FFEh

CH

0FFDh

BL

0FFCh

BH

CX

CH | CL

BX

BH | BL

SP2

0FFFh

CL

0FFEh

CH

0FFDh
0FFCh

0FFBh

0FFBh

0FFAh

0FFAh

0FF9h
8

1000h

0FF9h

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POP CX

POP BX

SP1

CX

CH | CL

BX

BH | BL

SP2

SP1

1000h
0FFFh

CL
CL

0FFEh

CH
CH

0FFDh

BL

0FFCh

BH

CX

CH | CL

BX

BH | BL

SP2

SP3

0FFFh

CL
CL

0FFEh

CH
CH

0FFDh

BL

0FFCh

BH

0FFBh

0FFBh

0FFAh

0FFAh

0FF9h
10

1000h

0FF9h

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SP1

CX

CH | CL

BX

BH | BL

SP1

1000h
0FFFh

CL

0FFEh

CH

0FFDh

BL

0FFCh

CX

CH | CL

BX

BH | BL

BH

C. Yehezkel

0FFFh

CL

0FFEh

CH

0FFDh

BL

0FFCh

BH

0FFBh

0FFBh

0FFAh

0FFAh

0FF9h
12

1000h

0FF9h
12

11

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11

PUSH EAX

:
PUSHF
POPF


16 .

POPF

POP EAX
]POP dword Ptr [EBX
POP DS

EFLAGS
13

32

EFLAGS
C. Yehezkel

POPA
POPAD
POPF
POPFD
15

Subroutine

CALL Target


RET

16

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16

:
. -
.
. -
- .

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14

16 bits
32 bits
POP reg 16 POP reg 32
POP mem POP mem 32
16
POP Seg

16

17

PushA
PushAD
PushF
PushFD

32

15

`PUSH `A

Push

16

C. Yehezkel

13

]PUSH dword Ptr [EBX

PUSH DS

Push mem 16 Push mem 32

Push Seg
Imm8,16,32

PUSHF

16
.

Push reg 32

Push reg 16

:
.1
.2

17

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18

instruction 1
instruction 2

Call

CALL
:

) IP (
,
.

IP
RET
CALL-

instruction 3
instruction 4
instruction 5

subroutine

RET

subroutine

19

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19

20

20

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Call

AX




65536

AX

Decision

subroutine

21

RET

subroutine

21

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22

PROC NEAR
PUSH AX
MOV AX,0
REPEAT: DEC AX
JNZ REPEAT
POP AX
RET
DELAY ENDP
DELAY

22

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:



AX




65536

AX

23

Push ax
Call delay

DELAY : PUSH AX
MOV AX,0
REPEAT: DEC AX
JNZ REPEAT
POP AX
RET

C. Yehezkel

DELAY: PUSH AX
MOV AX,0
REPEAT: DEC AX
JNZ REPEAT
POP AX
RET

23

24

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24

pseudoinstructions
.model small
KB 64 :
.stack 100h

.data

.code

**************;
mov ax,@data

mov ds,ax
+++
mov ah,4ch

int 21h
**************;
end

26

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26

. push pop-
.


\ .

Call
ret- .

27

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27

instruction

-

Interrupt Service Routine. ISR

.

:
INT

INT

IRE
T

29

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29

Timing of Interrupt signals

.1
.INT
.2
TF & IF
& IF
TF

data bus
INTA

CPU

I/O
INT
01
30

instruction
instruction

28

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28

ISR

instruction

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IF

.3 IP:CS
.


.INTA
.4

.


30
CS:IP

31

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31

ISR - IRET

, -
:

CS


IP


CS IP
.

.
.


CS


IP


\


Sti=set IF cli =clear IF


32

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32

IPL
IPH

0FFEh

CSL

0FFDh

CSH

0FFCh

FLAGS

0FFBh

FLAGS

0FFAh

IRET

SP_OLD

1000h
0FFFh

1000h

IPH | IPL

IP

CSH | CSL

CS

FLAGS

FLAGS

SP_NEW

0FF9h

IPL

0FFFh

IPL

0FFEh

CSL

0FFDh

CSH

0FFCh

FLAGS

0FFBh

FLAGS

0FFAh

SP_NEW

IPH | IPL

IP

CSH | CSL

CS

FLAGS

FLAGS

SP_OLD

0FF9h
34

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34

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33

INT

33

35

X86 External Interrupt Connections

INTR - Interrupt Request

35

C. Yehezkel

- INTR

Interrupt

Request

INT

.Data
Bus

8
Pointer

.4 ..12 .3

.6 .5

Interrupt
.type

Acknowledge
.

.Interrupt
number
- INTA.

.
.

NMI - Non-Maskable Interrupt

;IRR=0
IRR=1
ISR=1

Programmable
Interrupt Controller
)(part of chipset

NMI Requesting
Device
NMI
INTA

NMI

Intel

8086 CPU
INTR

Interrupt Logic

8259A

11110101

PIC
Single
Step

Divide
Error

Traps
36

C. Yehezkel

into

11110101
11110101

int

Software

11110101

DATA BUS
36

37

Yehezkel C.

" . .

37

39

Interrupts Terminology -

"Request" - IRQ occurs and indicates to CPU that it needs

attention

"Pending" - IRQ that is waiting to be serviced

"Service" - Process of executing the ISR

"Exception" - Higher priority event that can interrupt the
ISR (ex. RESET, Non-Maskable IRQ)

"Latency" - The delay between the "Request" and the
beginning of "Service"
Finish executing current instruction
Storing CPU registers to STACK
Retrieve ISR address from Vector Table
__________________________________ +
=Latency
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39

External interrupts are raised from outside the

CPU. (The mouse is an example of this type.)
Many I/O devices raise interrupts (e.g., keyboard,
timer, disk drives, CD-ROM and sound cards).

Internal interrupts are raised from within the
CPU, either from an error or the interrupt
instruction. Error interrupts are also called
traps.

Interrupts generated from the interrupt instruction
are called software interrupts.

DOS uses these types of interrupts to implement
its API (Application Programming Interface).
More modern operating systems (such as
Windows and UNIX) use a C based interface.
38

C. Yehezkel

into - INTO

Into Software
Interrupt
Interrupt Overflow
-OVERFLOW -
. OF=1
Divide
by 0 Interrupt

INTO Interrupt
Traps or
Error

. OVERFLOW CPU-

41

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41

In INTELx86 system, both exceptions and

interrupts are treated asinterrupts.

In MIPS system, exception is referred to all
unexpected events that cause the change of
control flow, while interrupt is restricted to
those unexpected events originating from
external devices.

40

0000:0001
0000:0002
0000:0003
0000:0004
0000:0005

Offset
Interrupt 0

IP MSB
CS LSB

Offset

0000:0006
0000:0007

Segment

YES

YES

INTR

Execute
ISR

IF=0
TF=0

pop
IP and CS

IF

Offset = Type 4

TF

Offset

Example:

int 36h

push
CS and IP

popf

Fetch
Next
Instruction

Offset = (544) = 216

= 00d8h

Segment
C. Yehezkel

acknowledge
interrupt

call
ISR

Read Type
Code #

NMI

Resume
Interrupted
Service
Procedure
???

Interrupt 255

0000:03fe

NO

0000:03fc

43

Set
TEMP=TF

NO

Given a Vector, where is the

ISR address stored in memory ?

0000:03ff

TEMP

NO

NMI

0000:03fd

YES

Internal
Interrupt

CS MSB

Interrupt 1

40

push
Flags

Complete
Current
Instruction

IP LSB

Segment

C. Yehezkel

IVT Format -
0000:0000

38

YES

NO

43

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42

Interrupt Vector Assignments

Type
0
1
2
3
4
5
6
7
8
9
A-F
10
11
12
13
14
15
16

Function
Divide Error
Single Step (DEBUG)
Nonmaskable Interrupt Pin
Breakpoint
Arithmetic Overflow
Print Screen Key
Invalid Opcode
Coprocessor Not Present
Time Signal
Keyboard Service
Originally Bus Ops (IBM PC)
Video Service Request
Equipment Check
Memory Size
Disk Service Request
Serial Port Service Request
Miscellaneous
Keyboard Service Request

45

Interrupt Vector Table IVT (in memory)

Comment
Processor - zero or overflow
Processor - TF=1
Processor - NMI Signal
Processor - Similar to Sing Step
Processor - into
BIOS - Key Depressed
Processor - Invalid Opcode
Processor - no FPU
BIOS - From RT Chip (AT - IRQ0)
BIOS - Gen Service (AT - IRQ1)
BIOS - (AT - IRQ2-7)
BIOS - Accesses Video Driver
BIOS - Diagnostic
BIOS - DOS Memory
BIOS - Accesses Disk Driver
BIOS - Accesses Serial Port Drvr
BIOS - Cassette, etc.
BIOS - Accesses KB Driver

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45

-
Pentium

x86 has 256 interrupts, specified by Type Number or Vector

1 byte of data must accompany each interrupt; specifies Type
Vector is a pointer (address) into Interrupt Vector Table, IVT
IVT is stored in memory from 0000:0000 to 0000:03ffh
IVT contains 256 far pointer values (addresses)
Far pointer is CS:IP values
Each far pointer is address of Interrupt Service Routine, ISR
Also referred to as Interrupt Handler

44

Type
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
2F
70-77

CSegment (High)
CSegment (Low)
IP (High)
IP(low)
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47

Function
Parallel Port LPT Service
ROM BASIC
Reboot
Clock Service
Control-Break Handler
User Timer Service
Pointer to Video Parm Table
Pointer to Disk Parm Table
Pointer to Graphics Fonts
Program Terminate
Function Call
Terminate Address
Control-C Handler
Fatal Error Handler
Absolute Disk Read
Absolute Disk Write
Terminate
Idle Signal
Print Spool
Hardware Interrupts in AT Bios

46

Similarity to Subroutine Procedure

Comment
BIOS - Printer Driver
BIOS - BASIC Interpreter in ROM
BIOS - Bootstrap
BIOS - Time of Day from BIOS
BIOS - Keyboard Break
BIOS - Timer Tick
BIOS - Video Initialization
BIOS - Disk Subsystem Init.
BIOS - CGA Graphics Fonts
DOS - Clear Memory, etc.
DOS - Transfer Control
DOS - program Terminate handler
DOS - For OS Use
DOS - Critical Error
DOS - Disk Read
DOS - Disk Write
DOS - TSR Usage
DOS - Idle
DOS - Cassette, etc.
DOS - (AT - IRQs 8-15)

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halt Instruction

call int
ret

44

Interrupt Vector Assignments Cont

INT n: Vector: n 4

47

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This instruction causes processor to enter a HALT state

iret

HALT state is one where no further instructions are fetched

call pushes CS, IP and loads CS:IP with address of

nor executed until one of the following events occurs:

subroutine

1) System is reset - rising edge on RESET pin

2) External interrupt occurs

INT does what CALL does and more

RET pops IP, CS
IRET pops FLAGS, IP, and CS
This is why ALL programs MUST have a stack segment, so

CPU Asset

Content

FLAGS Register

0000h

IP

0000h

CS

ffffh

DS

0000h

SS

0000h

ES

0000h

Instruction Queue

Empty

that interrupts can be handled

49

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48


Real -Mode -

POP PUSH

. -


.
CALL -

.RET
CALL

.
,


.ISR
, INT

.CALL
51

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. 1024

5

.Pentium 8086-
224

32 INTEL

.

51

50

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50

Computer Interrupt :

\
CPU

IN

IN AX, Port_Address (0-255)

I/O
IN AX, DX (>255)

Interrupt request: a signal that immediate attention is needed

Interrupt processing: what CPU does in response to request
Interrupt service: what is done in software as a result
2 General Types of Interrupts:
External - generated outside CPU by other hardware
Internal - generated within CPU as a result of instruction or operation
- x86 internals: int, into, divide error, and single step
- trap generally means any processor generated interrupt;
in x86, usually means the single step interrupt

Port DX

CPU

OUT

OUT Port_Address (0-255), AX

I/O
OUT DX (>255), AX

x86 Terminology for Interrupts:

1) Hardware Interrupt External, uses INTR and NMI control bus lines
2) Software Interrupt Internal, from int or into
3) Processor Interrupt traps, exceptions

Port DX

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55

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 Protected Mode -

USB Controller Disk Controller

:

IDT Interrupt Descriptor Table

256 * 8 Bytes

.

IDTR .
)IP (High
P |DPL|01110 00

Segment Selector
)IP (Low
56

16
57

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57

Call & Call Near -

Far

IRET -IRETD

IRET
Real- Mode - RET
.

IRETD

Protected Mode -
RET +EIP EFLAGS
.

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