Course No:

EEE 210

Group No: 09

Experiment No:

05

Name of The Experiment:

Part-A: STUDY OF JFET SMALL SIGNAL AMPLIFIER Part-B: STUDY OF THE BIASING AND FREQUENCY RESPONSE OF AN INTEGRATED CIRCUIT MOS AMPLIFIER

Date of Performance: Date of Submission:

05.06.2012 26.06.2012

Name: Kazi Mahmudur Rahman Roll:

1006033

Department: EEE

Level-2; Term-1
Partner's Name: Asif Ahmed Khan Partner's Student No: 1006032

PART-A
EXERCISE #1

FIG: Simulated circuit diagram with VSIN source

FIG: Circuit for AC sweep

FIG: Voltage gain vs Frequency

FIG: Voltage gain vs Frequency without capacitor Cs

FIG: Voltage gain vs Frequency with Cs removed and 100k added in series with source

FIG: Voltage gain vs frequency with Cs and RL=1 Meg

EXERCISE #2

FIG: Simulated circuit diagram for JFET as CD amplifier

FIG: Circuit for AC sweep

FIG: Voltage gain vs Frequency curve

PART-B
EXERCISE #3

FIG: Simulated circuit diagram with p -MOSFET and Rbreak= 10k

FIG: Simulated circuit diagram with p -MOSFET and Rbreak= 30k

FIG: Simulated circuit diagram with n -MOSFET and Rbreak= 10k

FIG: Simulated circuit diagram with n -MOSFET and Rbreak= 30k

EXERCISE #4

FIG: Circuit diagram

FIG: I R 2 vs Rbreak

FIG: Simulated circuit diagram with R3=(R*10k)

EXERCISE #5

FIG: Circuit diagram

FIG: I d vs V g s curve

FIG: Circuit diagram with VAC source

FIG: Output current vs Frequency curve

FIG: Normalized Voltage gain vs Frequency curve