RAJESH KUMAR BATHIJA

Contact address: C/o Shri Kashav Paliwal H.No. 41-42, Sect. 9A, Hiren Magri, Udaipur-313001 Mobiles :09414399891, 09413684841 Email: suharsh.rajesh@gmail.co m hodece@gits.ac.in

Paper Published

1. R.K. Bathija, GITS, Udaipur, R.S. Meena, UCE, RTU, KOTA S. Sarkar Jadhavpur University, Kolkata, Rajesh Sahu TINJRIT, Udaipur, Low Power High Speed 16x16 bit Multiplier using Vedic Mathematics. International Journal of Computer Applications (0975 8887) Volume 59 No.6, December 2012, Page No. 41-44. 2. Paper presented in National Conference on ICT: Theory, applications and practices during March 5 - 6, 2010 at SPSU, Udaipur on the topic A Pipline Systolic Architecture For A Kalman Filter Reconstruction Using CMOS Logic In 90 Nanometer Technology 3. Paper presented in National Conference (An In IEEE sponsored Arena conference) topic VLSI Innovative Signal Developments A Electronics For

organized by Arya Group Of College, Jaipur on December12,2009 on the Processing Gateway Wireless communication 4. Paper presented in National Conference on ICT: Theory, applications and practices during March 5 - 6, 2010 at SPSU, Udaipur on the topic A TV Ghost Canceller .
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Teaching Experience

More than 13 Years of Teaching Experience (Since Aug,02, 1999 to till date): Presently I am working in Gitanjali Institute of Technical Studies (GITS), Udaipur as an Asso. Proff. and HoD of the EC Deptt. from Nov. 21, 2012. Worked in Techno India NJR Institute of Technology (TINJRIT), Udaipur as an Asso. Proff. and HoD-EEE & EC deptt from April 26, 2012 to Nov. 20, 2012. Worked in Institute of Technology & Management (ITM), Bhilwara as an 2012. Worked in Mewar University (Self-financed State University), Gangrar, Chittorgarh as HOD of ECE Deptt (Asst. Professor in ECE deptt.) since Oct., 06,2009 to May 24, 2011. Also I am In-charge of B.Tech. III Year Students (Total 206 students). Worked in Mody Institute of Technology & Science, (Deemed-to Be University) Lakshmangarh as a Lecturer from July 2002 to Oct., 05, 2009. Worked as a Lecturer in Electronics Deptt. in B.M.A.S.Engg. College Agra (Sharada Group of Institutions) from 21st Aug. 2000 to 20th July 2002. Worked as a Lecture in Electronics Dept. in I.T.M. GWALIOR from 2nd Aug. 1999 to 19th Aug. 2000. Asso. Professor in ECE deptt., from June 01, 2011 to April 25,

School level Qualificatio n

EXAM. PASSED PERCENTAGE 10th II 12th I

BOARD DIV. M.P. Board

YEAR

1990

58.91 %

M.P. Board

1992

69.12 %

Technical Qualification
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DEGREE

DISCIPLIN E

BOARD/INSTITUTE

YEAR OF PASSING

PERCEN TAGE

B.E

Electronics & Telecommu nication VLSI DESIGN

Indira Gandhi Govt Engg College (Dr. H. S. Gaur Univ.) Sagar, M.P

1998

72.27%

M. E. (PartTime)

FET, MITS,Lakshmangarh Distt. Sikar Rajasthan

2009

8.34(CG PA)

PhD PhD Guide

Dissertatio n of M.Tech. Project of B.E.

Enrolled in RTU, KOTA on August 2011 with title VLSI implementation of Vedic Multiplier Dr. R.S. Meena, (Asso. Prof. RTU, Kota) Done Dissertation of M. Tech. (VLSI Design) in Reconstruction of signal using Kalman Filter in Domino Logic, Technology 90nm in the year 2008-09 under the supervision of Dr. Sankar Sarkar Sir MINOR: Made a photosensitive device for wrapper cutting machine in GODREJ SOAP Pvt. Ltd. MALANPURE, BHIND, and GWALIOR in 1998. MAJOR: To study the BRODBAND COMMUNICATION USING ASYNCRONOUS TRANSFER MODE in final year of B.E. On DSK TMS 320C6713,6414,5416,551 for DSP On Tanner Tools v12.6 for VLSI Design for layout and schematic design Active HDL for Verilog Programming FPGA Implementation Set Electronics Lab, Circuit Lab in ITM Gwalior from 1999 to 2000. Set Circuit Lab, Communication Labs in B.A.M.S. Engg. College from 2000 to 2002. Worked as a Board of Studies Secretary in MITS, Laxmangarh from 2005 to 2009. Worked as a Academic Councils Secretary in MITS, Laxmangarh from 2005 to 2009. Set Digital Signal Processing Lab, Circuit Lab, Communication Labs in MITS, Laxmangarh from 2002 to 2009 Guided several projects (18) in Mody College of Engineering. & Technology, Lakshmangarh, Sikar, Rajasthan. A few interesting are: 1) To make movable platform to reduce the time, waste in decelerate the train, boarding the train, accelerate the

Presently Working

Lab Developme nt & Project Guided

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train. 2) To save the life of driver & passengers from Head-OnCollision. 3) To save the life of a pedestrian from an accident. 4) Generating 16-point FET algorithm on DSK TMS320C6713. Attended workshop & Hands-on-Practice on VLSI Design at NIST, Behrampur,Orissa on 19-23 Oct., 2005, supported by Texas Instruments Worked as Secretary in a National level workshop organized by B.M.A.S. (Now HITM) Engg. College, Agra Worked as Technical Session Management Head in the National level Conference ETREE-12 organized by ITM Bhilwara form feb2526, 2012. Digital signal Processing & VlSI Design Operating Systems: Ms-DOS, Win9x, 2000. Computer Languages: C, C++, VHDL, Verilog HDL. Signal & system, DSP, VLSI,circuit theory, EDC, microwave, radar,

Workshop

Conferenc e Organizati on Area of Interest Computer Skills Subjects Taught

Personal Detail
Date of Birth Marital Status Nationality Wifes Name Mothers Name Father's Name References August 15, 1977 Married (2 sons) Indian Mrs. Poonam Bathija (PGT Chemistry, EGPS, Bhilwara) Late Mrs. KAUSHALYA BATHIJA (House Wife) Shri G. S. BATHIJA (Retd. High School Teacher) 1. Prof. S.N. Gupta (former professor from IIT, Delhi) Add: JECRC Engineering College, Sitapura, Jaipur Phone: 09460124570 2. Prof. S. Sarkar (former professor from IIT, Roorkee) Add: Shobhit University, Meerut Phone: 09458819002

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The information stated above is true to the best of my knowledge and spirit. (Rajesh Kumar Bathija)

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