ENGI 3861 Digital Logic

IV. COMBINATIONAL LOGIC DEVICES

(a) Programmable Logic Devices (PLDs)

PLDs devices with fixed logic configurations that be
programmed to implement a desired digital logic
functionality

- early devices were programmed by blowing fuses or can use
non-volatile memory cells to make connections

- first PLDs were programmable logic arrays (PLAs)
- example 43 PLA shown in Figure 6.21 from text
can have 6 4-input product terms for 3 outputs

e.g., consider O1 =I1I2I3 +I2I3
O2 =I1I3 +I1I2I3 +I2I3
O3 =I1I2 +I1I3 +I1I2I3

- use handout of Figure 6.22 from text to illustrate
implementation on 43 PLA

- commonly used PLD today is programmable array logic (PAL)

example PAL16L8 shown in Figures 6.25 (internal
structure) and 6.26 (block diagram indicating I/O)

- features: 16 inputs, 8 output (including 6 bidirectional I/O)
7 product (AND) terms for each output (not shared)
output enable gate controlled by 8
th
AND term

- a common high end PLD is called field programmable gate array
(FPGA) can be used to implement designs with millions
of gates
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ENGI 3861 Digital Logic
(b) Decoders

- general concept: map input codeword to output codeword

- in digital systems, a decoder is typically considered to be a
device that maps an n-bit binary codeword input to
1-out-of-2
n
output codeword n-to-2
n
binary decoder

e.g., 2-to-4 decoder (with enable (EN) input)

Inputs Outputs
EN I1 I0 Y3 Y2 Y1 Y0
0 X X
1 0 0
1 0 1
1 1 0
1 1 1









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ENGI 3861 Digital Logic
Why are decoders used?

typical application for decoder relates to addressing into
memory of computer system












- we can use decoders to implement n-bit Boolean function since
each output represents a minterm

- for example, a 2-to-4 decoder +OR gate can be used to
represent any 2-input gate

e.g., XOR







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ENGI 3861 Digital Logic


- e.g., Design majority vote circuit for 3 voters using a 3-to-8
decoder and OR gate.

truth table:

XYZ F
000 0
001 0
010 0
011 1
100 0
101 1
110 1
111 1










circuit:






- typical device is 74x138 3-to-8 decoder

see Figure 6.35, Table 6.6, and Figure 6.36

- large decoders can be built from smaller decoders

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e.g., Design a 5-to-32 decoder using 3-to-8 decoders.

3-to-8 decoder:









5-to-32 decoder:
















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ENGI 3861 Digital Logic
(c) Encoders

- 2
n
-to-n binary encoder is reverse of n-to-2
n
decoder, i.e., maps 2
n

bit input to n-bit output

e.g., 4-to-2 encoder









Inputs Outputs
I3 I2 I1 I0 Y1 Y0
0 0 0 1
0 0 1 0
0 1 0 0
1 0 0 0
All other input values.









of course, this does not deal with error conditions
e.g., 0110 Y1 Y0 =11
but Y1 Y0 should probably be 01 or 10 and not 11

- to resolve, can design priority encoder
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ENGI 3861 Digital Logic
e.g., 4-to-2 priority encoder assuming I3 has highest priority


IDLE =1
no inputs are high






Let Hi signal that is 1 if, and only if, Ii is highest priority input
that is high:

H3 = H2 =

H1 = H0 =

Y1 = Y0 =

IDLE =


- see text for 8-to-3 priority encoder

- example use of encoder is a positional encoder
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ENGI 3861 Digital Logic
(d) Multiplexers (Muxes)

- digital switch selects one of n data sources for output

block diagram:







e.g., 4-to-1 mux









Inputs Output
EN S1 S0 Y
0 X X 0
1 0 0 D0
1 0 1 D1
1 1 0 D2
1 1 1 D3








Y =

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ENGI 3861 Digital Logic
logic for mux:













mux symbol: mux concept:







- muxes can be used to implement Boolean functions

e.g., Implement a 2-input XOR using 4-to-1 mux



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ENGI 3861 Digital Logic
e.g., Implement the majority vote using 8-to-1 mux

truth table: circuit:











XYZ F
000 0
001 0
010 0
011 1
100 0
101 1
110 1
111 1



e.g., Implement the majority vote using 4-to-1 mux plus inverter (if
necessary)

F =

=





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ENGI 3861 Digital Logic
- muxes are primarily useful in digital systems for routing data

e.g., Consider the circuit of a 4-bit barrel shifter, which takes in 4
bits of data and rotates the positions of the bits by 0, 1, 2, or 3
positions to the left according to a two-bit control input, ROT

ROT Rotation Input Output
Y0 Y1 Y2 Y3
00 0 X0 X1 X2 X3
01 1 X0 X1 X2 X3
10 2 X0 X1 X2 X3
11 3 X0 X1 X2 X3
















Note: EN not shown, assumed that EN =1
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ENGI 3861 Digital Logic
Demultiplexer

- demux routes data from one input to one of several outputs

e.g., 1-to-4 demux diagram:




Inputs Outputs
EN S1 S0 Y3 Y2 Y1 Y0
1 0 0
1 0 1
1 1 0
1 1 1
0 X X


logic circuit of demux:

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ENGI 3861 Digital Logic
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(e) Three State (Tri-State) Devices

Consider







- 2 outputs trying to drive one input
will lead to problems if F1 =F2

- to solve can use a 3-state (tri-state) buffer/driver to allow outputs
to share line








where







also, other forms are


Note: we saw in PAL16L8 to achieve bidirectional I/O