EE2801 -- Lecture 19

An Introduction To The
PIC Microcontroller

EE2801-L19P01

The PIC 1

erie Microcontroller

The PIC Series of microcontrollers is representative of the current industry trend towards
highly capable, low-cost, processors for embedded applications. Although they are not
suited to everything, they can do a lot!

However, they are quite a bit different that what were used to at this point!

Some of the characteristics of the PIC 16F87X series are:

Only 35 instructions!
All instructions (except branch) execute in 1 cycle.
Eight level deep hardware stack.
4K word program space, 192 bytes of RAM
Internal A/D converter, serial port, digital IO ports, timers, and more!

Remember, what you are about to see will look completely different than anything youve
seen so far!

However, all of the techniques weve used and the concepts weve learned are directly
applicable!

EE2801-L19P02

The PIC 1

il C

ilitie

The following table summarizes the capabilities of the PIC16F87X series components.
Although when we use the compiler well set the processor type to 16F877, thats only
because each component in the family is compatible. The actual version well use is the
PIC16F874:

PIC1

Key Featu res

PICmi c ro

Mid-Range Referenc e

PIC16F873

PIC16F874

PIC16F876

PIC16F877

Operating Frequency

DC - 20 MHz

DC - 20 MHz

DC - 20 MHz

DC - 20 MHz

Resets (and Delays)

POR, BOR

POR, BOR

POR, BOR

POR, BOR

(PWRT, OST)

(PWRT, OST)

(PWRT, OST)

(PWRT, OST)

4K

4K

8K

8K

Data Memory (bytes)

192

192

368

368

EEPROM Data Memory

128

128

256

256

Interrupts

13

14

13

14

I/O Ports

Ports A,B,C

Ports A,B,C,D,E

Ports A,B,C

Ports A,B,C,D,E

Timers

Capture/Compare/PWM modules

MSSP, USART

MSSP, USART

MSSP, USART

MSSP, USART

Manu al (DS33023)

FLASH Program Memory

(14-bit words)

Serial Communications
Parallel Communications
10-bit Analog-to-Digital Module
Instruction Set

PSP

5 input channels

8 input channels

5 input channels

8 input channels

PSP

35 Instructions

35 Instructions

35 Instructions

35 Instructions

EE2801-L19P0

The PIC1 8 Architecture

13
FLASH
Program
Memory
Program
Bus

RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS

RAM Addr (1)

9
Addr MUX

Instruction reg
Direct Addr

PORTA

RAM
File
Registers

8 Level Stack
(13-bit)

14

Data Bus

Program Counter

PORTB
Indirect
Addr

FSR reg
STATUS reg

Instruction
Decode &
Control

OSC1/CLKIN
OSC2/CLKOUT

Timing
Generation

Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
In-Circuit
Debugger
Low-Voltage
Programming

PORTC

MUX
ALU

PORTD

RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT

W reg
RD7/PSP7:RD0/PSP0

Parallel Slave Port

PORTE
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS

MCLR VDD, VSS

Timer0

Data EEPROM

Timer1

CCP1,2

Timer2

Synchronous
Serial Port

10-bit A/D

Device

Program
FLASH

Data Memory

Data
EEPROM

PIC16F874
PIC16F877

4K
8K

192 Bytes
368 Bytes

128 Bytes
256 Bytes

USART

EE2801-L19P0

The PIC1 8 Pro r And t c Me or M

Instead of having a large memory space outside the processor and a small memory space
inside the processor (the registers) like we do in the 80x86, the PIC does two things. First,
it divides memory into two main spaces: program memory and data memory. For program
memory, the map looks as follows:

PC<12:0>

CALL, RETURN
RETFIE, RETLW

13

Stack Level 1
Stack Level 2

Stack Level 8

Reset Vector

Interrupt Vector

On-Chip

0000h

0004h
0005h

Page 0

07FFh
0800h

Program
Memory
Page 1

Note: The unused space in

this memory map is used in
other family processors.

0FFFh
1000h

1FFFh

EE2801-L19P0

The PIC16F874 Register File Map

FFh

A0h

Indirect addr.(*) 80h

OPTION_REG 81h
PCL
82h
STATUS
83h
FSR
84h
TRISA
85h
TRISB
86h
TRISC
87h
TRISD (1)
88h
TRISE (1)
89h
PCLATH
8Ah
INTCON
8Bh
PIE1
8Ch
PIE2
8Dh
PCON
8Eh
8Fh
90h
SSPCON2
91h
PR2
92h
SSPADD
93h
SSPSTAT
94h
95h
96h
97h
98h
TXSTA
99h
SPBRG
9Ah
9Bh
9Ch
9Dh
ADRESL
9Eh
9Fh
ADCON1

General
Purpose
Register

Indirect addr. (*) 00h

01h
TMR0
02h
PCL
03h
STATUS
04h
FSR
05h
PORTA
06h
PORTB
07h
PORTC
08h
PORTD (1)
09h
PORTE (1)
0Ah
PCLATH
0Bh
INTCON
0Ch
PIR1
0Dh
PIR2
0Eh
TMR1L
0Fh
TMR1H
10h
T1CON
11h
TMR2
12h
T2CON
13h
SSPBUF
14h
SSPCON
15h
CCPR1L
16h
CCPR1H
17h
CCP1CON
18h
RCSTA
19h
TXREG
1Ah
RCREG
1Bh
CCPR2L
1Ch
CCPR2H
1Dh
CCP2CON
1Eh
ADRESH
1Fh
ADCON0
20h
General
Purpose
Register

Bank 1

96 Bytes

7Fh

96 Bytes

Bank 0

File
Address
Indirect addr. (*) 180h
OPTION_REG 181h
PCL
182h
STATUS
183h
FSR
184h
185h
TRISB
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
PCLATH
INTCON
EECON1
EECON2
Reserved(2)
Reserved(2)

Indirect addr. (*) 100h

101h
TMR0
102h
PCL
103h
STATUS
104h
FSR
105h
106h
PORTB
107h
108h
109h
10Ah
PCLATH
10Bh
INTCON
10Ch
EEDATA
EEADR
10Dh
10Eh
10Fh
110h
EEDATH
EEADRH

accesses
A0h - FFh

Bank 3

1FFh

1EFh
1F0h

1A0h

17Fh

16Fh
170h

120h

accesses
20h-7Fh

Bank 2

EE2801-L19P06

e i ter
A ddr es
s

In The PIC Microcontroller

Value on:

Name

Bi t 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR,
BOR

Value on
all ot her
resets
(2)

Ba nk 0
(4)

00h

INDF

Addressing this location uses contents of FSR to address data mem ory (not a physical register)

01h

TMR0

Timer0 modules register

PCL

Program Counter's (PC) Least Significant Byte

(4)

02h

(4)

03h

(4)

STATUS

IRP

RP1

RP0

TO

PD

04h

FSR

05h

PORTA

06h

PORTB

07h

PORTC

PORTC Data Latch when written: PORTC pins when read

PORTD

PORTD Data Latch when written: PORTD pins when read

(5)

08h

(5)

09h

0Ah

0Bh

(1,4)
(4)

0Dh

PIR2

GIE

(3)

PSPIF

E2

RE0

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

EEIF

BCLIF

0Eh

TMR1L

Holding register for the Least Significant Byte of the 16-bit TMR1 register

0Fh

TMR1H

Holding register for the Most Significant Byte of the 16-bit TMR1 register

10h

T1CON

11 h

TMR2

12h

T2CON

13h

SSPBUF

RE1

Write Buffer for the upper 5 bits of the Program Counter

ADIF

(6)

CCP2IF

T1CKPS1

T1CKPS0

T1OSCEN

T1SYNC

TMR1CS

TMR1ON

TOUTPS2

TOUTPS1

TOUTPS0

TMR2ON

T2CKPS1

T2CKPS0

SSPM2

SSPM1

SSPM 0

Timer2 modules register

TOUTPS3

Synchronous Serial Por t Receive Buffer/Transmit Register

14h

SSPCO N

15h

CCPR1L

Capture/Compare/PWM Register1 (LSB)

WCO L

16h

CCPR1H

Capture/Compare/PWM Register1 (MSB)

17h

CCP1CON

18h

RCSTA

19h

TXREG

SPEN

SSPOV

RX9

SSPEN

CKP

SSPM 3

CCP1X

CCP1Y

CCP1 M3

CCP1 M2

CCP1 M1

CCP1M0

SREN

CREN

ADDEN

FERR

OERR

RX9D

CCP2 M3

CCP2 M2

CCP2 M1

CCP2M0

USART Transmit Data Register

1Ah

RCREG

USART Receive Data Register

1Bh

CCPR2L

Capture/Compare/PWM Register2 (LSB)

1Ch

CCPR2H

Capture/Compare/PWM Register2 (MSB)

1Dh

CCP2CON

1Eh

ADRESH

1Fh

ADCON0

CCP2X

CCP2Y

A/D Result Register High Byte

GO/
ADCS1

ADCS0

CHS2

CHS1

CHS0
DONE

0001 1xxx 000q quuu

xxxx
--0x
xxxx
xxxx
xxxx

PORTB Data Latch when written: PORTB pins when read

PIR1

PORTA Data Latch when written: PORTA pins when read

PCLATH

INTCON

Indirect data memory address pointer

PORTE

0Ch

0000 0000 0000 0000

xxxx xxxx uuuu uuuu
0000 0000 0000 0000

DON

xxxx
0000
xxxx
xxxx
xxxx

uuuu
--0u
uuuu
uuuu
uuuu

uuuu
0000
uuuu
uuuu
uuuu

---- -xxx ---- -uuu

---0 0000 ---0 0000
0000 000x 0000 000u
0000
-r-0
xxxx
xxxx
--00
0000
-000
xxxx
0000
xxxx
xxxx
--00
0000
0000
0000
xxxx
xxxx
--00
xxxx

0000
0--0
xxxx
xxxx
0000
0000
0000
xxxx
0000
xxxx
xxxx
0000
000x
0000
0000
xxxx
xxxx
0000
xxxx

0000
-r-0
uuuu
uuuu
--uu
0000
-000
uuuu
0000
uuuu
uuuu
--00
0000
0000
0000
uuuu
uuuu
--00
uuuu

0000
0--0
uuuu
uuuu
uuuu
0000
0000
uuuu
0000
uuuu
uuuu
0000
000x
0000
0000
uuuu
uuuu
0000
uuuu

0000 00-0 0000 00-0

EE2801-L19P0

o To e l ith All The e e i ter

R/W-0

R/W-0

R/W-0

R-1

R-1

R/W-x

R/W-x

IRP

RP1

RP0

TO

PD

DC

bit7

R/W-x
C
bit0

R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as 0

- n= Value at POR reset

bit 7:

IRP:
Register Bank Select bit (used for indirect addressing)

bit 6-5:

RP1:RP0: Register Bank Select bits (used for direct addressing)

1 = Bank 2, 3 (100h - 1FFh)

0 = Bank 0, 1 (00h - FFh)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes

bit 4:

TO: Time-out bit

bit 3:

PD: Power-down bit

bit 2:

Z: Zero bit

bit 1:

1 = After power-up, CLRWDT instruction, or SLEEP instruction

0 = A WDT time-out occurred
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit ( ADDWF, ADDLW,SUBLW,SUBWF instructions)
(for borrow the polarity is reversed)

bit 0:

1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
C: Carry/borrow bit ( ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note:

For borrow the polarity is reversed. A subtraction is executed by adding the twos complement of

the second operand. For rotate (

RRF, RLF) instructions, this bit is loaded with either the high or low order

bit of the source register.

EE2801-L19P08

An E

le PIC- ed

te

EE2801-L19P09