Tradeoff Design for Analog Integrated Circuits via

Geometric Programming
Li Dan*, Shu Guo-hua, Rong Meng-tian
Abstract - An approach of tradeoff design for analog
integrated circuits is presented Different from only one
specification is optimized in traditional approach, the
weighted sum of several performance specifications are
objective function of optimization in this approach. Each
weight factor is defined according to the specification's
importance to a designer. Then the optimal solution will be
the result of consideration for several performances.
Analysis of weighted factors effect on optimized
specifications is carried out. Hspice simulation result
proves the optimization is accurate.'
Index Terms - tradeoff design, analog K', geometric
programming, op amps

I. INTRODUCTION
Compared with design of digital integrated circuits,
automatic design of analog integrated circuits (IC) is far
away from satisfying. The one important reason is even one
little change of an element will affect the whole system.
Then the design of parameter values is a hard work.
Geometric programming is utilized in CMOS op amps
design [1], and also can solve the interconnect design
problems in many system-on-a-chip implementations [2].
The circuit parameters are automatically produced to get the
global optimal solution for minimum one specification
whereas fulfilling other performance requirements.
In analog IC design, the performance is characterized by
a number of specifications. These specifications restrict
each other mutually.
For example, an op amp has
performance measures such as open-loop voltage gain,
quiescent power, input-referred noise, output voltage swing,
unity-gain bandwidth, input offset voltage, common-mode
rejection ratio, slew rate, die area, and so on. When one
specification is optimized, some of other specifications often
become worse. For example, low power dissipation design
will introduce slow response speed. Sometimes we need
take several specifications into account and make a tradeoff
choice.
1 This work was sponsored by Shanghai-Application Material (AM)
Research Foundation (08700740700)
Li Dan is with School of Electronic, Information and Electrical
Engineering, Shanghai Jiao Tong University, 200240, China(e-mail:
lidan@sjtu.edu.cn)
Shu Guo-hua is with School of Electronic, Information and Electrical
Engineering, Shanghai Jiao Tong University, 200240, China(e-mail:
shuguohua@sjtu.edu.cn)
Rong Meng-tian is with School of Electronic, Information and Electrical
Engineering, Shanghai Jiao Tong University, 200240, China(e-mail:
rongmt@sjtu.edu.cn)

978-1-4244-3870-9/09/$25.00 2009 IEEE

824

In this paper, we presented a method to get a tradeoff

design of a two-stage op amp with a new frequency
compensation technique via geometric programming. By
this method, the objective function to be optimized is not a
specification, but the weighted sum of several important
specifications.

II. GEOMETRIC PROGRAMMING

The basic theory of geometric programming was
presented by Duffm and Zenor in 1967 [3]. In 1994,
Nesterov and Nemirovsky developed an efficient interiorpoint algorithm to solve a variety of nonlinear optimization
problems [4]. This algorithm is suitable for geometric
programming and a significant improvement in
computational efficiency was achieved. The geometric
programming has two splendid merits. Firstly, problems
with hundreds of variables and thousands of constraints are
handled in seconds by personal computer; secondly, the
found solution is always global, regardless of the starting
point. If constraints are too strict to get any solution, the
algorithm will reply "No solution". Two-stage op amps
optimal design via geometric programming is analyzed in
[5].
The defmitions of geometric programming involved
following concepts.
Xl' X 2 , , X n are n real, positive variables to be designed,

CD Monomial function
g(X 1,X2 , ,x n) = CX~1 X~2 .. x:n
Where

(1)

aI' ..., an could be any real.

is positive real,

Posynomial function
A sum of one or more monomials,
K

f(xl'x 2 , ,xn ) = LCkX~lkX:2k X:1k

(2)

k=l

Where ck is positive real, the term 'posynomial' is meant

to suggest a combination of 'positive' and 'polynomial'.
Any monomial is also a posynomial when K = 1 .
Posynomials are closed under addition, multiplication, and
positive scaling.
Standard form of geometric program
Optimization variables:
Minimize:

Xl' X 2 ' , x n

fa (x)

subject to: h(x) ~ 1, i = 1, ....m

gi(X) = 1, i = 1, ...,p
Xi > 0 , i = 1,..., n

(3)
(4)
(5)

That means our purpose is minimize functionfo(x) , and

the constraints are given by equations (3), (4), (5).
fo(x) and [(x) are posynomial functions and gi(X) is
monomial functions.

III. TRADEOFF DESIGN

In previous application of geometric programming, we
gave ranges of many specifications, and then optimize only
one performance, e.g. the minimum quiescent power or the
maximum unity-gain bandwidth. However, sometime we
would like to tradeoff between several specifications. Not
much quiescent power increasing is acceptable if the unitygain bandwidth has significantly improved.

The optimization solution in this step is that minimum

quiescent power Pmin It is 2.3mw.
Step 2: Search the maximum unity-gain bandwidth via
conventional approach. Now we just give a range of
quiescent power that it should be less than 5mw. The unitygain frequency Ie is

Ie =sqrt(~2J1pCoxI}(~/L}))/(21iCc)

(7)

Cox is the capacitance per unit area; Jlp is channel

mobility of PMOS; ~/L} is the ratio of width to length

of M} . But I} is not a optimization variable, and we
know Is = 2I} , so the objective function is

Ie =sqrt(~J1pCoxIs(~/L}))/(21iCc)

(8)

The optimization solution in this step is that maximum

unity-gain frequency Fmax It is 89 MHz.
Step 3: make compromise between the two specifications,
sum = k} x power/ Pmin + k2 xFmax / Ie
(9)
The k} and k2 are weight coefficients according to the
specifications importance for the designer. If the first
specification is more important than the second one to the
designer, k} should be larger than k2 .We give different
values to k} , k2 , the results are shown in Table I. Analysis
is shown in Table II. We defined weighted quiescent power
increased percentage (PIP) and unity-gain frequency
decreased percentage (FIP) to measure changes of the two
specifications.

I
I

---------------

Frequency compensation is necessary for two-stage op

amps. There are three kinds of compensation circuits [6]. In
this example, we design a new circuit structure for
frequency compensation. We hope it with low quiescent
power and high unity-gain bandwidth. These two
requirements are contrary. We have to fmd a balance point
for them. Tradeoff design is used to calculate the parameter
values.
The required specifications are given at left column of
Table IV. The channel length L is determined by
fabrication techniques. There are 17 optimization
variables. They are the widths of 12 MOS transistors W;,
( i = 1,2 12 ), the compensation capacitor C; and

the

bias current of the current source I bias' the drain currents

flowing through transistors I}}, 17 ,and Is .Some constraints
of geometric programming could be found in [5].
The steps of tradeoff design:
Step 1: Now we just limited that the unity-gain frequency
should be more than 50M. Search the minimum quiescent
power via conventional approach, the objective function is
power dissipation.
power = VDD(Ibias +1 11 +Is +17 )
(6)

(10)

PIP = (power - Pmin ) / Pmin

Fig. 1. The diagram of a two-stage op amp with a new frequency

compensation technique

FIP = (Fmax

Ie) / F

(11)

max

When k} = 0, k2 = 1 , it is conventional approach only

optimize unity-gain frequency. Though the unity-gain
frequency is maximized, the quiescent power increases
115%. When k} = 0.5, k2 = 0.5, it is tradeoff design taking
power and Ole into account .Though the unity-gain
frequency decrease 27%, the quiescent power only
increases 27%.
TABLE I
WEIGHTED COEFFICIENTS AND OPTIMIZED QUIESCENT POWER, UNITYGAIN FREQUENCY

kl

k2

Quiescent power

Unity-gain frequency

4.9mw

89M

2.3mw

50M

0.5

0.5

2.9mw

65M

0.6

0.4

2.6mw

58M

0.4

0.6

3.3mw

71M

We choose the solution when k, = 0.5, k2 = 0.5 .The

simulation results are shown in right column of Table IV.
They are approximately equal to tradeoff design solution in
Table I. Table IV shows that the design fulfills all the
required performance requirements.
825

TABLED
WEIGHTED COEFFICIENTS AND OPTIMIZED QUIESCENT POWER
INCREASED PERCENTAGE (PIP), UNITY-GAIN FREQUENCY DECREASED
PERCENTAGE (FDP)

kl

k2

Weighted sum

0
0

PIP

FDP

115%

0%

0%

44%

0.5

0.5

1.30

27%

27%

0.6

0.4

1.17

14%

35%

0.4

0.6

1.30

44%

20%

IV.

CONCLUSION

Analog Ie parameters design is a hard task. Their values

of global solution can be calculated via Geometric
programming. By tradeoff design presented in this paper, a
solution balanced in several specifications was found. This
approach can be applied in all analog designs to simplify the
process and achieve satisfying design.
REFERENCES

[1]

[2]

[3]
[4]
[5]

[6]

M. H. Maghami, F. Inanlou, R. Lotfi, "Simulation-equation-based

methodology for design of CMOS amplifiers using geometric
programming," Electronics, Circuits and Systems, 2008. ICECS 2008.
vol. 3, pp:360-363, 2008
W. T. Cheung, N. Wong, "Power optimization in a repeater-inserted
interconnect via Geometric Programming," Low Power Electronics
and Design, ISLPED'06. pp:226-231,2006
R. J. Duffin, E. L. Peterson, C. Zener, Geometric programming-theory
and application. New York, USA: Wiley, 1967.
Y. Nesterov, A. Nemirovsky, Interior-point polynomial methods in
convex programming. Philadelphia, USA: SIAM, 1994
M. M. Hershenson, S. P. Boyd, T. H. Lee, "Optimal design of a
CMOS op-amp via geometric programming," Computer -Aided
Design of Integrated Circuits and Systems, vol. 20, pp. 1-20, January
2001
A. D. Grasso, G. Palumbo, S. Pennisi, "Comparison of the frequency
compensation techniques for CMOS two-stage miller OTAs". Circuits
and Systems II: Express Briefs,vol. 50, pp : 1099-1103,2008

TABLE III
THE OPTIMIZED VARIABLE VALUES (kl

0.5,k2 = 0.5)

variable

value

Cc

3.79j.1F

15

0.246mA

17

0.342mA

i:

0.032mA

~=W2

225j.1m

~=~

112.75j.1m

Ws

45.7j.1m

W6

312.8j.1m

n;

63.4j.1m

Wg

5.95j.1m

9. 86j.1m

W.O

2.465j.1m

~l

Zum

W.2

156.4j.1m

TABLE IV
REQUIRED SPECIFICATIONS AND SIMULATION RESULT VIA HSPICE
Required Specifications

Minimize:

sum = k1 x power/Pmin

Simulation Result via HSPICE

Quiescent power: 2.908m W

Unity-gain frequency:65M

+ k2 xFmax/OJc
Output voltage
rang: [0.1,0.9]VDD
Open-loop gain z 80dB

Output voltage rang:

[0.03,0.9]VDD

Open-loop gain:

81.3dB

Phase margin z 600

Phase margin: 64

Common-mode rejection

Common-mode rejection

ratio ;;:::90dB
Slew rate z 10V / j.1S

826

ratio:95 dB
Slew rate:18 V / us

Input-referred spot

Input-referred spot noise,

noise, 1kHz ~ 300nV/ Jih

1kHz :282 nV/ Jih