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Pattern Generation

Rolf Drechsler, Grschwin Fey

University of Bremen

drechsle@informatik.uni-bremen.de

Outline

Introduction/Motivation

Preliminaries

Circuit, Fault Model, Test Pattern Generation

Proof techniques

Boolean satisfiability, BDD, SAT, Circuit to SAT

Conversion

SAT-based ATPG

Problem description

Multi-valued Encoding

Variable Selection

Experimental Results

Conclusions

2

Motivation

Source: Intel

Motivation

Increasing size of circuits

Post-production test is a crucial step:

Have there been problems during

production?

Does the circuit contain faults?

Test patterns are applied

4

Motivation

Test pattern generation happens at the

Boolean level

Classical ATPG algorithms reach their

limits

There is a need for more efficient ATPG

tools!

Circuits

Basic gates

AND, OR, EXOR, NOT

AND

OR

XOR

NOT

Fault Model

Model realistic fault

Physical faults or defects at the

Boolean level

Simplified assumption

Based on netlist

Static or dynamic

Here: static only

7

Single line is assumed to have a fixed

value (0 or 1)

Example: stuck-at 0 fault at line d

correct

faulty

a

a

b

c

d

f

e

d

0

e

8

Physical defects are modeled on the

Boolean level

Stuck-at-0

Inputs

Output

Given:

Objective:

Calculate test patterns for

faults in C with respect to F

Boolean Difference

BD of faulty and fault free circuit

a

b

d

f

e

BD

d

0

e

10

Fault Classification

If there is a test, the fault is testable.

If there does not exist a test, the fault

is redundant.

Decision is NP complete.

11

ATPG: D-Algorithm

An error is observed due to differing values at a line in

the circuit with or without failure. Such a divergence is

denoted by values D or D to mark differences 1/0 or

0/1, respectively.

Instead of Boolean values, the set {0,1,D,D} is used to

evaluate gates and carry out implications.

A gate that is not on a path between the error and any

output does never have a D-value.

A necessary condition for testability is the existence of a

path from the error to an output, where all intermediate

gates either have a D-value or are not assigned yet.

Such a path is called a potential D-chain.

A gate is on a D-chain, if it is on a path from the error

location to an output and all intermediate gates have a

D-value.

12

General Structure

Justification and Propagation

Fault site

Justification

Propagation

Reconvergent path

13

Improvements

FAN: branching on fanout stems

SOCRATES: learning

HANIBAL: recursive learning

Alternative: SAT-based

Formulation based on formal

techniques

Proof techniques: BDD and SAT

14

Representation

Truth table

SoP (DNF) and PoS (CNF)

Examples

Sum-of-products

F = x1x2x3 + x1x2x3 + x1x2x3

Product-of-sums

F = (x1+x2+x3) (x1+x2+x3)

(x1+x2+x3) (x1+x2+x3) (x1+x2+x3)

Decision tree

15

16

Rule 1: Isomorphism Rule

Nodes must be unique

(I-reduction)

Redundant tests should not

be present (S-reduction)

17

Decision Tree

reduction

BDD

18

Shannon Expansion

A Boolean function can be expanded by

Shannon

F(x,y,z) = x Fx + x Fx

where Fx and Fx are positive (negative) cofactors

Fx = F(0, y, z), Fx = F(1, y, z)

19

If-Then-Else-Operator:

ITE(F, G, H) = F G + F H

Boolean operations over ITE arguments can be

expressed as ITE of F, G, and constants

Example: AND(F, G) = ITE(F, G, 0)

Computation of Boolean operations is based on the

Shannon expansion:

ITE(F,G,H) = ITE(x, ITE(Fx,Gx,Hx), ITE(Fx,Gx,Gx))

20

10

Example:

F=ac+bc+d

G=ac+d

F+G = ?

21

Example:

F=ac+bc+d

G=ac+d

F+G = a+bc+d

reduction

22

11

Properties

Efficient implementation

Compact representation for many

Boolean functions

Polynomial manipulation algorithms

Sensitive to variable ordering

NP-complete problem

Dynamic variable ordering

23

Function Representation

BDD-based representation of

- functions (with dont cares)

- relations

- minterms, cubes

- sets (of sets)

- state machines

- ...

Common features of all successful BDD-based

representations

24

12

Simulation

Application of values

1

1

Fast computation

linear time

Complete simulation only feasible for small

circuits

exponential in the number of inputs

25

Symbolic Simulation

Application of variables

One computation for all

input patterns in

parallel

Construction of

diagrams for each gate

synthesis

operations

Size of diagrams

26

13

SAT

Often all patterns are not needed

A single test-vector is sufficient

Construction of satisfying assignment

SAT-problem: For a given Boolean

function f find an assignment a, such

that f(a)=1 or prove that such an

assignment does not exist.

27

SAT

real problem

real solution

(a + b + c ) ( a + c )

(b + c ) ( c + d )

(c + d ) ( d + e + f )

( d + f ) (e + f ) f

SAT instance

a = 0,b = 0,

c = 0, d = 1

e = 1, f = 1

SAT solver

SAT solution

28

14

29

CNF of a Gate

d = [d = (a b)]

= [d (a b)]

= [(a b)d + a b d]

= [a d + b d + a b d]

= (a + d)(b + d)(a + b + d)

30

15

=h

(a + d)(b + d)(a + b + d)

(b + e)(c + e)(b + c + e)

(d + f)(d + f)

(d + g)(e + g)(d + e + g)

(f + h)(g + h)(f + g + h)

assignment h=1

31

SAT Solving

Most Algorithms are based on DLL

procedure

Overall flow

Assign variables in the CNF

If a contradiction occurs

backtrack

32

16

Basic Procedure

33

Implications

Unit clause: Only one unspecified literal

=

(a + b + c)

1

c=0

on iteration of unit clause rule

BCP corresponds to

implications on the net list

Fast implementation, since

CNF is very regular

34

17

Implications

Analysis of backtracks

Decision heuristics

Conflict learning

Instance grows

Non-chronological backtracking

Data structure

CNF

Circuit

35

DLL An Example

(a+c+d)

(a+c+d)

(a+c+d)

(a+c+d)

(a+b+c+d)

0

0

36

18

DLL An Example

(a+c+d)

(a+c+d)

(a+c+d)

(a+c+d)

(a+b+c+d)

0

0

37

DLL An Example

(a+c+d)

(a+c+d)

(a+c+d)

(a+c+d)

(a+b+c+d)

0

0

38

19

DLL An Example

(a+c+d)

(a+c+d)

(a+c+d)

(a+c+d)

(a+b+c+d)

0

0

1

0

0 0

39

DLL An Example

(a+c+d)

(a+c+d)

(a+c+d)

(a+c+d)

(a+b+c+d)

0

0

1

0

0 0

40

20

DLL An Example

(a+c+d)

(a+c+d)

(a+c+d)

(a+c+d)

(a+b+c+d)

0

0

1

0

0 0

41

DLL An Example

(a+c+d)

(a+c+d)

(a+c+d)

(a+c+d)

(a+b+c+d)

0

0

1

0

0 0

0 b

d

1

42

21

BDDs consider all solutions

SAT finds single solution

Backtrack tree similar to BDD structure

Advanced SAT techniques:

Variable selection strategies

Efficient implementations

Engineering

Implications

Conflict analysis

43

Substantial improvements in SAT

solving

Use

Advanced SAT techniques

In combination with structural

information

For

Large industrial circuits

In a multi-valued domain

44

22

CORRECT

Inputs

Output

!

BD = 1

FAULTY

x

Stuck-at-0

Output

45

SAT-based ATPG

Input: Circuit C, Fault F

1. Fault modeling:

BD between fault free and faulty circuit

2. Translate into CNF

3. Use SAT solver to calculate solution

Output: Classification of F, Testvector T

46

23

Circuit CNF

a

b

c

AND-gate:

OR-gate:

(a+b+d) (a+d) (b+d)

47

Influenced circuit parts

Fault site

Cone of

Influence

Fault Shadow

48

24

Create Instance

Build circuit structure accordingly

Fault free

1

Faulty

49

Fault modeling

a

a

b

c

dg

b

c

eg

BD

e

df

ef

a

b

dg

50

25

CNF

a

b

c

a

b

dg

eg

df

ef

BD

dg

(a +b + dg) (a + dg) (b + dg) (df)

(c +df + ef) (c+ef) (df+ef)

(eg+ef+BD) (eg +ef +BD)

(eg +ef+BD) (eg +ef +BD) (BD)

F is the CNF for circuit with d s-a-1

Inputs satisfy CNF can detect fault

CNF is linear in circuit size

51

Use approach as in D-algorithm

Gate G on path between fault and output:

unfaulty circuit:

Gg = G(Xg)

faulty circuit:

Gf = G(Xf)

G on a D-chain implies

difference:

Gd (Gf Gg)

at least one successor is on the

D-chain: Gd (H1,d +... + Hk,d)

52

26

CORRECT

Inputs

Gg

Gd

!

BD = 1

FAULTY

SA-0

x

Gf

H1,f

H2,f

H3,f

53

Features of PASSAT

Memory Management

Advanced SAT techniques

Problem specific variable selection

Multi-valued model

54

27

Built-in techniques from Zchaff

Conflict based learning

Non-chronological backtracking

Event-driven evaluations

Clever decision heuristics

55

SAT Run Times for Redundant Faults

56

28

Variable Selection

Use problem specific strategies to chose

next decision variable

Only inputs

In

Only fanouts

Zchaffs default strategy

Combined strategy

First: Only inputs with time-out

Then: Zchaffs default

Out

57

Variable Selection

Use problem specific strategies to chose

next decision variable

Only inputs

In

Only fanouts

Zchaffs default strategy

Combined strategy

First: Only inputs with time-out

Then: Zchaffs default

Out

58

29

Variable Selection

Use problem specific strategies to chose

next decision variable

Only inputs

In

Only fanouts

Zchaffs default strategy

Combined strategy

First: Only inputs with time-out

Then: Zchaffs default

Out

59

Variable Selection

Use problem specific strategies to chose

next decision variable

In

Only fanouts

Zchaffs default strategy

Combined strategy

First: Only inputs with time-out

Then: Zchaffs default

Out

60

30

Heuristic

Cnt

Red

Ab

Time(s)

All

255

3847

Input

187

67

1787

Fanout

256

2568

Input+All

187

68

2084

61

Multi-valued Model

Application to industrial circuits

Allow for Z and U values

Encode circuit lines by two variables

Optimize the encoding

62

31

Multi-valued Model

Encoding

Clauses for

c=ab

63

natural

64

32

65

Experimental Results

66

33

circuit

<0.1

0.1-1

1-10

10-20

abort

P44k

57

19

P49k

385

1581

P80k

207

P88k

106

167

P177k

137

119

58

13

P565k

961

440

67

Circuit

Cnt

Red

Ab

Eqn (s)

SAT (s)

P44k

61230

823

17821

30797

P77k

126338

1156

334

P80k

176159

7420

5591

P88k

126929

2354

169

2985

9044

P99k

131913

759

4548

4364

36965

P565k

1175605

26372

28343

1456

3073

68

34

Challenges/Future Work

Use of advanced SAT techniques

incremental SAT

Optimization of SAT instance

Boolean reasoning during creation

Other fault models

dynamic model, e.g. path delay

faults

69

Conclusions

Formulation based on formal techniques

Use of structural information

Advanced SAT techniques

Multi-valued circuits

Applicable to large industrial circuits

70

35

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