EEE5026; 943/U0280

Physical Design for Nanometer ICs

Yao-Wen Chang
ywchang@ntu.edu.tw
http://cc.ee.ntu.edu.tw/~ywchang
Graduate Institute of Electronics Engineering
Department of Electrical Engineering
National Taiwan University
Spring 2016

Administrative Matters
Time/Location: Thursdays 2:20 pm--5:30 pm; BL-114
Instructor: Yao-Wen Chang
E-mail: ywchang@ntu.edu.tw
URL: http://cc.ee.ntu.edu.tw/~ywchang
Office: BL-428. (Tel) 3366-3556; (Fax) 2364-1972
Office Hours: Wednesdays 56pm; other times by appointment
Teaching Assistant: Zhi-Wen Lin (lzw@eda.ee.ntu.edu.tw); office
hours: 12:301:30pm, Wednesdays
Prerequisites: data structures, algorithms, and logic design
Required Text: Either of the following two books:
Wang, Chang, and Cheng (Ed.), Electronic Design Automation:
Synthesis, Verification, and Test, Morgan Kaufmann, 2009
Sait and Youssef, VLSI Physical Design Automation: Theory and
Practice, World Scientific Publishing Co., 1999

References: Selected reading materials from recent publications

Unit 1

Y.-W. Chang

Teaching Assistant

Zhi-Wen Lin
Email: lzw@eda.ee.ntu.edu.tw
Office: BL-406;
Tel: 23635251 # 6406
Office Hours: 12:30-1:30pm,
Wednesdays.
2nd-year Ph.D. student

Unit 1

Y.-W. Chang

Y.-W. Chang
3

Course Objectives

Study techniques/algorithms for physical design

(converting a circuit description into a geometric

description) and their comparisons
Study nanometer process/electrical effects and their
impacts on the development of physical design tools
Study problem-solving (-finding) techniques!!!
solution S1
S2
S3
S4
S5
P1 P2 P3 P4
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P5 P6

problem
4

Course Contents
VLSI design flow/styles and technology roadmap
Physical design processes
Partitioning
Floorplanning
Placement
Routing (global, detailed, clock, and power/ground routing)
Post-layout optimization
Signal/power integrity: crosstalk, IR drop
Timing: timing modeling, performance-driven design
Design methodology: large-scale design, interconnect-centric
design flow, buffer/wiring planning.
Design for manufacturability & reliability
process variation, antenna effect, redundant via, optical
proximity correction (OPC), chemical mechanical polishing
(CMP), multiple pattering, e-beam, EUV, directed self-assembly
(DSA), nanowire, electromigration, thermal issues, etc.

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Grading Policy

Grading:

Homework assignments + quizzes: 25%

Programming assignments + lab: 25%
One in-class open-book, open-note exam: 30% (June 9)
Final project + presentation + demo: 20% (due June 23)
A 1-page project proposal is due in-class on May 19
Could be research work, implementation, and/or literature
survey

Default project: Problem C, D, or E of the 2016 IC/CAD Contest at

http://cad-contest-2016.el.cycu.edu.tw/

Teamwork is permitted (1--3 persons; preferably 2 persons)

Bonus for class participation

Homework: 20% per day penalty for late submission

WWW: http://cc.ee.ntu.edu.tw/~ywchang/Courses/PD/pd.html
Academic Honesty: Avoiding cheating at all cost
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Unit 1: Introduction

Course contents:

Introduction to VLSI design flow/styles

Introduction to physical design automation
Semiconductor technology roadmap

Readings

W&C&C: Chapter 1
S&Y: Chapter 1
physical
design

Unit 1

fabrication

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IC Design & Manufacturing Process

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From Wafer to Chip

2, 4, 6, 8-inch wafers

8-inch vs. 1-inch ignot

12-inch wafer
Apple A8 die (iPhone 6)
TSMC 20nm process;
2B+ transistors

18-inch wafer

Wafer dicing

Wire
bonding

chips
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IC Design Considerations

Several conflicting considerations:

Unit 1

Complexity: large number of devices/transistors

Power: low-power consumption
Performance: high-speed requirements
Cost: die area, packaging, testing, etc.
Time-to-market: about a 15% gain for early birds
Others: manufacturability, reliability, testability, etc.
Y.-W. Chang

10

Moores Law: Driving Technology Advances

Logic capacity doubles per IC at a regular interval (say, 18 months).

G. Moore: Logic capacity doubles per IC every two years (1975).

D. House: Computer performance doubles every 18 months (1975)
4Gb
Itanium 2

Intel uP

4004

Unit 1

8086

80386

PentiumPro

Y.-W. Chang

Pentium 4

Itanium 2

11

Design Productivity Crisis

100,000K

1,000M
100M
10M

10,000K

58%/yr compound
complexity growth rate

Complexity
limiter

1,000K
100K

1M

10K

0.1M

21%/yr compound
1K
productivity growth rate

0.01M
1980

0.1K

1985

1990

1995

2000

2005

Productivity in transistors
per staff-month

Logic transistors per chip

10,000M

2010

Human factors may limit design more than technology.

Keys to solve the productivity crisis: CAD (tool &
methodology), hierarchical design, abstraction, IP
reuse, platform-based design, etc.

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Old (1997) Technology Roadmap for Semiconductors

Source: International Technology Roadmap for Semiconductors (easier to

see the past & trend with the older version; for more recent update, see
http://www.itrs.net/).
Deep submicron technology: node (feature size) < 0.25 m.
Nanometer Technology: node < 100 nm.
14/16 nm technology was in production in 2015.

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Nanometer Design Challenges

Intel Core i7-2600: feature size 32 nm, P frequency

3.4 GHz, die size 81 mm2, P transistor count per chip

382M, wiring level 10+ layers, supply voltage 1.3 V,
power consumption 95 W (full load)

Unit 1

Feature size : sub-wavelength lithography (impacts of

process variation)? reliability? noise? wire coupling?
Frequency , dimension : interconnect delay?
electromagnetic field effects? timing closure?
Chip complexity : large-scale system design
methodology?
Supply voltage : signal integrity (noise, IR drop, etc)?
Wiring level : manufacturability? yield? 3D layout?
Power consumption/density : power & thermal issues?

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14

Design Complexity Increases Dramatically!!

Mixed-size Placement

Routing & interconnect

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Power Is a Key Limiting Factor for IC Design!

Power density increases exponentially!

1000

Power doubles every 4 years

5-year projection: 200W total, 125 W/cm2 !

Rocket
Nozzle

Watts/cm

Nuclear Reactor
100

Pentium 4

Itanium 2
10

Power & Performance

trade-off!!

Pentium Pro
Pentium

i386

Itanium 2-DC

Pentium III
Pentium II

Hot plate

i486
1

Fred Pollack, New Microarchitecture Challenges in the Coming Generations of CMOS

Process Technologies, 1999 Micro32 Conference keynote. Courtesy Avi Mendelson, Intel.
Y.-W. Chang

Interconnect Dominates Circuit Performance!!

70

Worst-case
interconnect
delay due
to crosstalk

60

Delay (ps)

50
40
30

Interconnect
delay

20
10

Gate delay
650

500

350

250

180

150

100

Source: Synopsys

Technology Node

In 0.18m wire-to-wire
capacitance dominates (CW>>CS)
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CS

70 (nm)

CW
17

Manufacturing with Optical Lithography

Patterns on a mask are transferred onto a wafer

Light source
Illumination
Lens
Mask
Projection

Lens

Immersion
(water)

Wafer

R = k1 / NA

0.25 * 193 nm / 1.35 = 36 nm

R: resolution; k1: resolution constant (>= 0.25); : wavelength

NA: numerical aperture = f(lens, refractive index)
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18

Sub-Wavelength Lithography Gap

Sub-wavelength lithography: use light of larger

wavelength (193nm) to print features of smaller sizes

EUV
E-beam
[S. Borkar, MICRO04]
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19

Technology Roadmap [Aitken, 2014]

EUV + DSA
eNVM

NEMS
EUV LELE

Patterning

VNW
SAQP

Log (complexity)

Interconnect

CNT
Opto

monolithic
TSV

EUV + DWEB

MLG, CNT
LELELE
III-V

Transistors

SADP

EUV
HNW

FinFET
LELE

We Are Here

HKMG
Strain
PMOS

Planar CMOS

NMOS

Strong RET
LE, <

LE, ~
CU wires

AI wires

1975

1985

10nm 7nm 5nm 3nm

1995

2005

2015

2025

Source: R. Aitken @ ISPD14 Keynote & S. Segars @ 2014 Kaufman Award dinner
(with revision by Y.-W. Chang)
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20

Most Expected Patterning Technologies

Multiple patterning
lithography (MPL)

Extreme ultraviolet
lithography (EUVL)

Electron beam
lithography
(EBL)

Directed SelfAssembly (DSA)

Each technology has different difficulties and

requires solutions for a breakthrough
Y.-W. Chang

Litho-Etch-Litho-Etch (LELE) Double Patterning

Pro: Simpler layout decomposition into masks

Con: Overlay error with misalignment between masks
40nm
20nm

20nm

+
mask 1

mask 1

mask 2

20nm 80nm

80nm

mask 2

1st exposure-etching process

photoresist
mask
Target film
substrate

2nd exposure-etching process

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22

Extreme Ultraviolet Lithography (EUVL)

EUVL is the most invested next-generation lithography

technology

Its wavelength is only 13.5 nm

Reflective optical components and masks are used
Reflective
mask
Reflective illuminator
optics (mirrors)
Reflective projection
optics (mirrors)

EUV source

Wafer

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23

Electron Beam Lithography (EBL)

EBL is a maskless next-generation lithography technology

Maskless: no more diffraction limitation of light

Can define very fine patterns

Mapper Lithography
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24

Directed Self-Assembly (DSA)

Block copolymer DSA for contact/via patterning

Groups of contacts/vias are patterned by guiding templates

with traditional 193i lithography

Self-assembly
block copolymer

Topographical and
chemical patterns

Mask
Smaller and denser patterns

Template

Contacts

Contact patterning with DSA

Contact patterns formed by various DSA templates

[Xiao, et al., ASP-DAC15]
Y.-W. Chang

Cut/Via Pattering with DSA

A large template can be used to pattern multiple close

contacts even for sub-7nm nodes

Layout

close vias

Vias

Templates
22nm

7nm
[Xiao, et al., DAC14]
Y.-W. Chang

Reliability Becomes a 1st-Order Effect!!

Reliability with 10-layer metal?

m5
m4

+
++

m3

+ +++

m2
m1

sgd

Unit 1

Si substrate

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sgd

27

3D Integration Adds Complexity!

2.5D packaging technology and through-silicon vias (TSV)

for Xilinxs 28nm 7 series FPGAs vs. 3D integration

3D integration
device

TSV

substrate

2.5D interposer integration

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dielectric

routing
region

28

Traditional VLSI Design Cycles

1.
2.
3.
4.
5.
6.
7.

System specification
Functional design
Logic synthesis
Circuit design
Physical design
Fabrication
Packaging
Other tasks involved: verification, simulation, testing, etc.
Design metrics: area, speed, power dissipation,
manufacturability, reliability, testability, design time, etc.
Design revolution: interconnect (not gate) delay dominates
circuit performance in deep submicron era.

Unit 1

Interconnects are determined in physical design.

Shall consider interconnections in early design stages.
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29

Traditional VLSI Design Cycle

& verification

& verification

& simulation

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30

Traditional VLSI Design Flow (Cont'd)

design

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31

Physical Design (PD)

physical
design

fabrication

PD converts a circuit description into a geometric description.

The description is used to manufacture a chip.
Physical design cycle:

Unit 1

1. Partitioning
2. Floorplanning
3. Placement
4. Routing (clock, power/ground, signal nets)
5. Post-layout optimization (buffering, sizing, etc.)
Others: circuit extraction, timing verification and design rule
checking
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32

Physical Design Flow

B*-tree based floorplanning system

Routing system
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33

Floorplan Examples

Apple A5
with dual
ARM cores

Intel
Pentium 4

A floorplan
with
interconnections

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34

VLSI Placement

Place objects into a die s.t. no objects overlap with each

other & some cost metric (e.g., wirelength) is optimized
chip
ISPD98 ibm01

12,752 cells
247 macros
Amax/Amin = 8416

842K cells
646 macros
868K nets

wirings among cells/macros are not shown here!!

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35

Routing Example
0.18um technology, two layers, pitch = 1 um, 8109 nets.

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36

Modern EDA & Circuit Design Challenges

Multi-dimension

Scalability

Heterogeneity

Technology

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Example: Modern Placement

High complexity

2.5M
placeable
objects

Millions of objects
Scalability

mixed-size
design

Placement constraints

Blockage, routability,
density, timing, region, etc.

Macros have
revolutionized
SoC design

Multi-dimension

Mixed-size placement

Thousands of big macros

with millions of small cells
Heterogeneity

device
TSV

TSV

More: 3D IC, datapath, FPGA,

etc.

dielectric
routing region
substrate

Technology
Y.-W. Chang

Design Styles

Others

Power

Structure ASIC

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FPGA SPLD

39

SSI/SPLD Design Style

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40

Full-Custom Design Style

Designers can control the shape of all mask patterns.

Designers can specify the design up to the level of individual

transistors.

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41

Terminology

Cell: a logic block used to build larger circuits.

Pin: a wire (metal or polysilicon) to which another
external wire can be connected.
Nets: a collection of pins which must be electrically
connected.
Netlist: a list of all nets in a circuit.
nets

cells

pin

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42

Standard-Cell Design Style

Selects pre-designed
cells (typically, of the same
height) to implement logic

Over-the-cell routing is
pervasive in modern
designs

Modern designs often

contain cells of different
row heights (esp. with
FinFET transistors)

Unit 1

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43

Standard Cell Example

Courtesy of Newton/Pister, UC-Berkeley

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44

Gate Array Design Style

Prefabricates a transistor array

Needs wiring customization to implement logic

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45

FPGA Design Style

Logic and
interconnects are
both prefabricated.

Illustrated by a
symmetric arraybased fieldprogrammable
gate array (FPGA)

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46

FPGA/CPLD Examples
Xilinx XC4413 FPGA (0.35 um)

Altera FLEX 6000 CPLD (0.3 um)

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FPGA Design Process

Illustrated by a symmetric array-based FPGA

No fabrication is needed

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Comparisons of Design Styles

Full
custom

Standard
Cell

Cell size

variable

fixed height

fixed

fixed

Cell type

variable

variable

fixed

programmable

Cell placement

variable

in row

fixed

fixed

variable

variable

programmable

Interconnection variable

Unit 1

Gate
array

FPGA

Full
custom

Standard
Cell

Fabrication time

---

--

+++

Packing density

+++

++

---

Unit cost (large quantity)

+++

++

---

Unit cost (small quantity)

---

--

+++

Easy design & simulation

---

--

++

Easy design change

---

--

+++

Timing simulation accuracy

--

++

Chip speed

+++

++

---

Y.-W. Chang

Gate
array

FPGA

49

Design Style Trade-offs

10

full
custom

10
Turnaround
Time
(Days)
2
10

semicustom

SPLD

10

FPGA

CPLD

optimal
solution

SSI
1
1

10

10

10

10

10

10

10

10

Logic capacity (Gates)

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50

Appendix:

Structured ASIC

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51

Structured ASIC
A structured ASIC consists of predefined metal and via layers, as
well as a few of them for customization.
The predefined layers support power distribution and local
communications among the building blocks of the device.
Advantages: fewer masks (lower cost); easier physical extraction
and analysis.
Popular for engineering change orders (ECOs)

A structured ASIC
(M5 & M6 can be customized)
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Faradays 3MPCA structured ASIC

(M4--M6 can be customized)
52

Comparisons of Design Styles

Full
custom

Standard
Cell

Cell size

variable

fixed height

fixed

fixed

fixed

Cell type

variable

variable

fixed

fixed

programmable

Cell placement

variable

in row

fixed

fixed

fixed

variable

variable

variable/fixed

programmable

Interconnection variable

Gate
array

Full
custom

Standard
Cell

Fabrication time

---

--

Packing density

+++

Unit cost (large quantity)

Structure
ASIC

Structure
ASIC

FPGA

++

+++

++

---

+++

++

---

Unit cost (small quantity)

---

--

+++

Easy design & simulation

---

--

++

Easy design change

---

--

+++

Timing simulation accuracy

--

++

Chip speed

+++

++

---

Unit 1

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Gate
array

FPGA

53