Lausanne Basic Slides1

Basics of Low Power Circuit and Logic Design
Anantha Chandrakasan
Massachusetts Institute of Technology
High Performance Processors

Microprocessor Power
(source ISSCC)
Power (Watt)
30
20
10
0
75
80
85
Year
90
Anantha Chandrakasan 1997
95
Portable Devices
Required
Portable Functions
Radio transceiver
Modem
Voice I/O
Pen Input
Battery
(40+ lbs)
Text/Graphics Processing
Text/Graphics display
Video decompression
Full-motion video display
How to get 8 hours of operation ???

Nominal Capacity (Watt-hours / lb)
Battery Trends
50
Rechargable Lithium
40
Ni-Metal Hydride
30
20
Nickel-Cadmium
10
0
65
70
75
80
Year
85
90
95
(from Jon Eager, Gates Inc. , S. Watanabe, Sony Inc.)

Where Does Power Go in CMOS?

Dynamic or switching currents
- Charging and discharging parasitic capacitors
Short-circuit or direct-path currents

- Direct path between supply rails during switching
Leakage currents
- Reverse bias diode leakage
- Sub-threshold conduction
Static currents
Dynamic Power of a CMOS Gate

Vdd
E0->1 = CLVdd2
A1
AN
PMOS
NETWORK
NMOS
NETWORK
isupply
Vout
CL
Vdd
T
T
E 0 1 = P ( t )dt = V dd i supply ( t )dt = V dd C L dV out = C L V dd 2
0
0
0
Vdd
T
T
1
2
E cap = P cap ( t )dt = V out i cap ( t )dt = C L V out dV out = --- C V dd
2 L
0
0
0
Modification for Circuits with Reduced Swing

Vdd
Vdd
Vdd -Vt
CL
E 0 1 = C L V dd ( V dd V t )
Can exploit reduced swing to lower power

(e.g., reduced bit-line swing in memory)
Physical Capacitance of an Inverter
Capacitance, fF
50.0
Cjunction + Cgate
40.0
30.0
Cjunction
20.0
Cgate
10.0
0.0
0.8
1.0
1.2
1.4
1.6
1.8
2.0
VDD
Important to account for capacitive non-linearities

in power estimation
Node Capacitance is a Function of Voltage
Switched Capacitance, fF
110
100
LCLR
90
80
TSPCR
70
C2MOS
60
50
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
VDD, V
Node Transition Activity and Power

Consider switching a CMOS gate for N clock cycles
E N = C L V dd 2 n ( N )
EN : the energy consumed for N clock cycles
n(N): the number of 0->1 transition in N clock cycles
EN
2
n(N)
P avg = lim -------- f clk = lim ------------ C V dd f clk
N N
N N
L
0 1 =
n( N)
lim -----------N N
P avg = 0 1 C V dd 2 f clk
L
10
Factors Affecting Transition Activity, 0->1

Static component (does not account for timing)
Type of Logic Function (NOR vs. XOR)
Type of Logic Style (Static vs. Dynamic)
Signal Statistics
Inter-signal Correlations
Dynamic or timing dependent component

Circuit Topology
Signal Statistics and Correlations
11
Type of Logic Function: NOR vs. XOR

Example: Static 2 Input NOR Gate
Out
Assume:
p(A=1) = 1/2
p(B=1) = 1/2
Then:
p(Out=1) = 1/4
p(01)
= p(Out=0).p(Out=1)
= 3/4 1/4 = 3/16
Truth Table of a 2 input NOR gate
0->1 = 3/16
12
Type of Logic Function: NOR vs. XOR

Example: Static 2 Input XOR Gate
Out
Assume:
p(A=1) = 1/2
p(B=1) = 1/2
Then:
p(Out=1) = 1/2
p(01)
= p(Out=0).p(Out=1)
= 1/2 1/2 = 1/4
Truth Table of a 2 input XOR gate
0->1 = 1/4
13
Type of Logic Style: Static vs. Dynamic

Vdd
Vdd
A
CLK
CL
CL
CLK
Power is only dissipated when Out=0!

STATIC NOR
DYNAMIC NOR
0->1 = 3/16
N0
3
0 1 = ------- = --4
N
2
14
Another Logic Style: Dynamic DCVSL

Vdd
Vdd
OUTB
OUT
IN
INB
I
Guaranteed transition for every operation!

0->1 = 1
15
Influence of Signal Statistics on 0->1
B
2
p0->1 .1
0.6
PB
0.4
0
0
CL
0.8
0.2
0.4
PA
pa
0.2
0.6
0.8
pb
10
p1 = (1-pa) (1-pb)
p0->1 = p0 p1 = (1-(1-pa) (1-pb)) (1-pa) (1-pb)
0->1 is a strong function of signal statistics

16
Inter-signal Correlations
A
A
Z
(a) Logic circuit without

reconvergent fanout
(b) Logic circuit with

reconvergent fanout
p0->1 = (1- pa pb) pa pb = 3/16
pZ = p(C=1|B=1) p(B=1)
p0->1 = 0
Need to use conditional probabilities to model

inter-signal correlations!
CAD tools required for such analysis
17
Dynamic or Glitching Activity in CMOS
Cin
Add0
Add1
Sum Output Voltage, Volts
S0
Add2
Add14
S2
S14
S1
4.0
Add15
S15
S15
6
2.0
S10
Cin
5
S1
0.0
2
5
10
Time, ns
0->1 can be > 1 due to glitching!

18
Glitch Reduction Using Balanced Paths

F
A0
A1
A2
A3
A4
A5
A6
A7
Ripple
A0
A1
A2
A3
A4
A5
Lookahead
A6
A7
19
Comparison of Adder Topologies

Power-Delay-Product-1
16 bit
32 bit
64 bit
Ripple Carry
3.09
0.81
0.27
Carry Lookahead
10.0
3.54
1.76
Carry Bypass
5.45
2.39
0.99
Carry Select
4.44
2.08
1.00
Conditional Sum
3.82
1.23
0.42
Logic Transition Histogram
from [Callaway92]
(VLSI Signal Processing, V)
20
Glitching at the Datapath Level

A
B C
Tree vs. Chain
(A + B) + (C + D)
(A + B) + C + D
Inputs Normalized # of Transitions

Tree
Chain
1.45
2.5
Can be reduced by reducing the logic depth and balancing

signal paths
21
Short-circuit Component of Power

Vdd
Vin
Vout
CL
IVDD (mA)
0.15
0.10
0.05
0.0
1.0
2.0
3.0
Vin (V)
4.0
5.0
22
Short-Circuit Current vs. Load Capacitance
from [Veendrick84]
(IEEE Journal of Solid-State Circuits, August 1984)
23
Minimizing Short-circuit Power

0.5
E / E(tRin=0)
0.4
0.3
Device Sizes:
W/LP = 7.2m/1.2m
W/LN = 2.4m/1.2m
Vdd = 5V
0.2
0.1
0.0
0.0
Vdd = 3V
0.5
1.0
tRin/tRout
1.5
2.0
Keep the input and output rise/fall times the same

(< 10% of Total Consumption)
from [Veendrick84]
(IEEE Journal of Solid-State Circuits, August 1984)
If Vdd < Vtn + |Vtp| then short-circuit power can be eliminated!

24
Reverse Biased Diode Leakage

GATE
p+
Reverse Leakage Current

+
V
- dd
IDL = JS A
JS = 1-5pA/m2 for a 1.2m CMOS technology
Js double with every 9oC increase in temperature
25
Subthreshold Leakage Component

10-2
10-3
10-4
10-5
ID , A
10-6
VT = 0.1V
10-7
VDS=1V
ID
VT = 0.4 V
10-8
VGS +-
10-9
10-10
10-11
10-12
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VGS, V
Leakage control is critical for low-voltage operation

26
Static Power
Vdd
Istat
Vin=5V
Vout
CL
Pstatic = p(In=1).Vdd . Istat
Not a function of switching frequency
27
Ultra Low Power System Design

System
Design partitioning, Power Down
Algorithm
Complexity, Concurrency, Locality,

Regularity, Data representation
Architecture
Concurrency, Instruction set selection,

Signal correlations, Data Representation
Circuit/Logic
Transistor Sizing, Logic optimization,

Activity Driven Power Down,
low-swing logic, adiabatic switching
Technology
Threshold Reduction,
Advanced packaging
Lower Supply Voltage and Switched Capacitance

28
Signal Processing Attributes

Throughput constrained computing
- 30ms refresh rate requirement for video
- Optimize power supply voltages
Time-varying computational requirements

- Adaptive signal processing techniques
4000
Speech Data
water all year

2000
0
-2000
-4000
Time
Transition Probability
Knowledge of signal statistics

0.7
0.6
Sign-extension
0.5
0.4
0.3
0.2
0.1
0.0
10
Bit Number
15
29
Energy Efficiency Metric: Fixed Throughput

Example: Video Compression
P = ( (NiCiVdd2)) fsample
Energy/Sample
fsample is fixed
For this mode (most DSP applications), minimizing
energy/sample is both Energy and Power Efficient
30
Energy Efficiency Metric: Max Throughput

Process
Queue
from [Burd95]
(HICSS 95)
Energy/operation
Power
ETR ------------------------------------------- = ----------------------------------2Throughput
Throughput
A lower ETR (higher efficiency) indicates lower energy
for constant throughput, or higher throughput for
constant energy
Other metrics such as E x D,

see [Horowitz94],
(1994 Symposium on Low-power Electronics)
31
NORMALIZED DELAY
Supply Voltage Scaling

7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
multiplier
2.0m technology
CL Vdd
Td =
I
clock generator
I ~ (Vdd - Vt)2
ring oscillator
Td(Vdd=1.5)
microcoded DSP chip
Td(Vdd=5)
adder
adder (SPICE)
2.0
4.0
(1.5) (5 - 0.7)2
(5) (1.5 - 0.7)2
8
6.0
Vdd (volts)
Lowering Vdd reduces energy but increases delays

32
Technology Based Voltage Scaling
Vdd
Vout
Vout
CL
0.9Vdd
VDSAT
0.1Vdd
Fall Time:
Vin
Vin
2
1 +
V
1 const. dd
-1
time
from [Kakumu90]
(IEEE Tran. on Electron Devices)
Power Supply Voltage: Vdd(V)
Exploit velocity saturated sub-micron devices to lower

voltage without significant loss in device speed
Technology based Optimal Vdd: 2.43V for 0.3m CMOS
33
Supply Voltage Scaling Using VT Reduction

1.5
1.25
VDD,V
1.0
tpd=645pS
tpd=420pS
0.75
tpd=840pS
0.5
0.25
0.0
0.05
0.15
0.25
0.35
0.45
VT, V
Threshold voltage reduction enables voltage scaling

without performance loss
34
Optimizing Continuous Mode Circuits

1.25
tpd=420pS
Energy (pJ)
1.00
VDD=1.02V
VDD=1.4V
0.75
VDD=0.55V
0.50
VDD=1V
VDD=0.67V
VDD=0.34V
tpd=840pS
0.25
0.0
0.05
0.15
0.25
VT (V)
0.35
0.45
Optimum VDD/VT point trades-off switching and

leakage power and is a strong function of activity
also see [Burr94]
35
Limits of Supply Voltage Scaling

CMOS Inverter Transfer Curves
Vout
0.7
0.6
Output Voltage (V)
0.6
0.5
0.5
0.4
0.4
Experiment
0.3
0.3
0.2
0.7 V = Vs
Calculation
0.2
0.15
0.1
0.1
0
0.2
0.2
0.3
0.4
0.5
Input Voltage (V)
0.6
0.7
Vin
Vsmin 2-4 kT / q
from [Swanson72]
(IEEE JSSC, April 1972)
36
Burst Mode or Event DrivenComputation

BLOCKED
(waiting for
hardware events
and client requests)
RUNNING
(doing actual
computation)
Trunning
Tblocked
On
Off
Trace
1
Trace
2
Trace
3
Trace Length (sec)
5182.48
26859.9
995.16
Toff (sec)
5047.47
26427.4
960.82
Ton (sec)
135.01
432.5
34.34
Toff/(Toff+Ton)
0.9739
0.9839
0.9655
For an X-server application, processor spends most of the

time in the blocked or off state.
from [Srivastava95]
(IEEE Trans. on VLSI Systems)
37
Techniques for Burst Mode Computation

High VT
SLEEP
Multiple VT Technology
Low VT
(Disable high VT devices during idle periods)

e.g., [Sakata93] (Symposium on VLSI Circuits),
[Mutoh93] (International ASIC Conference)
SLEEP
High VT
High VT transistor sizing issues

Preserving state requires extra transistors
38
Latch Design in MTCMOS
SLEEP
SLEEP
High VT
High VT
SLEEP
High VT
SLEEP
High VT
CLK
From S. Mutoh, et. al.

JSSC, August 1995
39
Techniques for Burst Mode Computation

VDD
ON
+ VP > 0
standby
Vout
Vin
Substrate Bias Controlled

Variable VT Devices (Increase VT during idle periods)
standby
ON
from [Seta95] (ISSCC 1995)
+
- VN < 0
Needs large body factors - large well capacitances

Triple well process needed
40
SOI with Active Substrate (SOIAS)

tfox
n+
n+
p+
Loverlap
SiO2
p+
i-poly
tsi
tbox
p+
SiO2
n+
SiO2
Silicon Substrate
Backgate Control Enables

Dynamically Varying Threshold Voltages
from [Yang95]
41
NMOS Device Characteristics

10
Vt=0.448 V (Vgb=0.0 V)
Vt=0.184 V (Vgb=3 V)
-2
10-3
0.03
10-4
1.8x
10-6
10
10-8
0.02
Leff=0.44 um
tsi=4.5 nm
tfox=9 nm
tbox=100 nm
VDS=1.0 V
-7
~ 4 Dec
10-9
10-10
Id (mA/um)
Id (mA/um)
10-5
0.01
10-11
10-12
10-13
0
-0.2
0.2
0.4
0.6
0.8
Vgf (V)
42
Ring Oscillator Frequency (MHz)
Ring Oscillator Characteristics

12
Varied VTN only
VTP= - 0.2V
10
6
0.0
Varied VTP only

VTN = 0.512V
0.1 0.2 0.3 0.4 0.5 0.6 0.7

Backgate Controlled Variable |VT| (V)
Processor speed is adjustable on demand

43
Architectural Model & Activity Parameters for SOIAS

Add15
Add1
a
b
Circuit Node Transition Activity
x
4
.2
0.6
PB
0.4
0
0
0.2
0.4
PA
CLK
ADD
CLK BACKGATE
0.2
0.6
pa
CLK ADD
0.8
0.8
pb
10
10
ADD OFF
ADD ON
ADD ON
fga = Module Activity Factor

CLK
BACKGATE
LOW VT
HIGH VT
LOW VT
bga = Backgate Switching Activity

44
Generic Architecture Model for All Technologies
Leakage Control
Mechanism
(hence affecting bga)
Technology
Multiple Threshold Technology
Switching the High VT

devices ON/OFF
Substrate Bias Control
Controlling the
Substrate Voltages
Silicon On Insulator Active Substrate
Switching the
Backgate Voltage
Hierarchy of Profilers and Statistical Models

Required for Virtual Prototyping
45
Energy Estimation Models for SOI and SOIAS

fga = Module Activity Factor
bga = Backgate Switching Activity
= Node Transition Activity Factor
ESOI = fga CfgVdd2

+ Ileak_lowVT Vdd Tcycle
ESOIAS = fga CfgVdd2
+ fga Ileak_lowVT Vdd Tcycle
+ (1-fga)Ileak_highVT Vdd Tcycle
+ bgaCbgVbg2
46
Architectural Profiling to Determine fga and bga

Table 1. SPEC benchmark espresso
Total Instructions
Additions
Shifts
Multiplications
Number
fga
bga
900158847
543616709
57000715
172883
0.6039
0.0633
0.0002
0.1954
0.0541
0.0002
Number
fga
bga
1737729538
661236960
52224367
7088
0.6023
0.0087
0.0000
0.2233
0.0086
0.0000
Number
fga
bga
2125
1250
186
3
0.5882
0.0875
0.0014
0.2635
0.0753
0.0014
Table 2. SPEC benchmark Li

Total Instructions
Total Additions
Total Shifts
Multiplications
Table 3. Data Encryption (IDEA)

Total Instructions
Additions
Shifts
Multiplications
47
SOI vs. SOIAS Technology Evaluation
Adder
0.5
Shifter
**
0.0
1
-0.5
-1.0
**
1
.
ac
tiv
ity
1.5
2
4
fac
tor
)
2
2.5
3.5
2.5
log(fron
t-gate ac2 1.5 1
tivity fac
tor)
log
(b
ac
kga
te
log(ESOIAS/ESOI)
Mult.
.
3.5
0.5
48
Transistor Sizing for Low-Power

Lower Capacitance
Higher Voltage
Small W/Ls
Large W/Ls
Higher Capacitance
Lower Voltage
Larger sized devices are useful only when interconnect dominated

Minimum sized devices are usually optimal for low-power
49
Transistor Sizing for Fixed Throughput

Cg = W/L CMIN
I W/L CMIN
CMIN = Minimum sized gate (W/L=1)

W /L after sizing
CP = Cwiring + CDF
= CP / (K CMIN)
HIGH PERFORMANCE
W/L >> CP / (K CMIN)
LOW POWER
W/L = 2 CP / (K CMIN)
(if CP K CMIN)
ELSE W/L = 1
NORMALIZED ENERGY
10
7
=0
5
4
= 0.5
3
2
=1
1.5
adder
1.0
0.7
= 1.5
=2
0.5
from [Chandrakasan92]
(IEEE JSSC, 1992)
W/L
10
50
Capacitance Breakdown
MODULE LEVEL
MODULE
GATE
DIFFUSION
INTERCONNECT
ADDER (Conventional Static)
30%
45%
25%
ADDER (Carry Select)
37%
31%
32%
TSPC COUNTER
32%
26%
36%
LOG SHIFTER (8 bit shift by 4)
15%
42%
43%
COMPARATOR
33%
38%
29%
DATAPATH LEVEL
MODULE
GATE
DIFFUSION
INTERCONNECT
ADDER CHAIN ( 7 adders )
38%
38%
24%
WAVE DIGITAL FILTER
31%
29%
40%
ADDRESS GENERATION (STD CELL)
56%
24%
20%
VIDEO SYNC GENERATOR

(STD CELL)
45%
25%
30%
51
Choice of Logic Style

B
VDD
A A
B B
A
B
VDD
VDD
A
B
SUM
Cout
CIN
A
GEN
CIN
COUT
COUT
CIN
GEN
GEN
GND
A CC
VDD PRE VDD
CIN
B
PROP
OPTIMIZED static Adder
SUM
CIN
GND
COSUM
GND
VDD
CIN
GEN
VDD
CIN
CIN
VDD PRE VDD
CIN
GEN
CONVENTIONAL CMOS Adder
CO
CIN
Sum
GND
CIN
C
B
B
C
VDD
CIN
A
A
B
B
C
C
A
A
CIN
A
Sum
DCVSL Adder
Sum
Cout
Cout
CPL Adder
52
Choice of Logic Style

200
POWER-DELAY PRODUCT (pJ)
150
8-bit adders in 2.0m
Standard Cell
100
70
50
30
20
DCVSL
15
10
7
5
Optimized
Static
Decreasing Vdd
CSA
Conventional
Static
CPL - LOW Vt
3
10
30
100
DELAY (ns)
Power-delay product improves as voltage decreases.

The best logic style minimizes power-delay for a given
delay constraint.
53
Reducing the Energy/Operation at a Fixed Vdd
Heavily
Loaded
Bit-line
Vdd (=1.5V)
M1
M2
o 6/2 3/9 o
V(out)
M5
<
Vin
M4
9/2
7/2
M3
Volts
o
Vout
v(out)
Ceff = 5pF
v(out)
1.0
Signal
Amplification
>
4/2
v()
1.5
v(line)
0.5
0
20
40 60
t (ns)
80 100
Reduced Signal Swing Example: FIFO Memory
Power Reduction Over Rail-to-Rail Swing = Vdd/(Vdd-Vt)
54
Reducing the Energy/Operation at a Fixed Vdd

R
tr
ADIABATIC CHARGING
E = (RC/tr)CV2
(for tr >> RC)
Applying slow input slopes reduces E below CV2

Useful for driving large capacitors (Buffers)
Power reduction > 4 for pad drivers (1 MHz) ISI
55
Example: Stepwise Adiabatic Driver

VN
V2
V1
RC charging steps
from [Svensson94]
CL
(IEEE Symposium on Low Power Design, 1994)
Vi = (i/N) V
2
1
--- C L V dd
V dd V dd
2
E step = Q V avg = C L ---------- ---------- = --------------------------------N
2N
2
N
2
1
--- C L V dd
E conventional
2
E total = N --------------------------------- = ---------------------------------------2
N
N
56
Activity Driven Logic Level Power Down

A[N-1]
MSB
REG
B[N-1]
MSB
COMPARATOR
A>B
CLK
A[N-2:0]
COMBINATIONAL
REG
BLOCK
CLK
LOGIC
REG
for
bits
0->N-2
MODIFIED REGISTER
B[N-2:0]
REG
for
bits
0->N-2
COMPARATOR
A>B
for
bits 0->N-2
CONDITIONALLY
SWITCHED
GATED_CLK
from [Alidina94]
(1994 International Workshop on Low-power Design)
50% reduction possible for random inputs

57
Activity Reduction in Shift Registers

N Length Shift Register
Data In
Data Out
fCLK
Pserial = NCreg V2 fclk

N/2 Length Shift Register
Data In
Data Out
fCLK/2
Pparallel= 2 x (N/2 Creg V2 fclk/2) + Poverhead

58
Shift Register Power for Various Lengths
Normalized Power Dissipation
1.0
0.8
32-bit
0.6
0.4
64-bit
128-bit
0.2
0.0
256-bit
0
16
Degree of Parallelism
24
32
59
Summary
Power dissipation is a prime design constraint for
portable systems
Low Power design requires optimization at all Levels
Sources of power dissipation have been analyzed
Technology, circuit, and logic design techniques have
been described
60
References
[Alidina94] M. Alidina, J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou, Precomputation-Based Sequential Logic
Optimization for Low Power, 1994 International Workshop on Low-power Design, pp. 57-62, April 1994.
[Burd95] T. Burd, R. Brodersen, Energy Efficient CMOS Microprocessor Design, Proceedings of the 28th Annual HICSS Conference, Vol. I, pp. 288-297 Jan. 1995.
[Burr94] J. Burr, J. Shott, A 200mV Self-Testing Encoder/Decoder using Stanford Ultra-low Power CMOS, IEEE ISSCC, pp.
84-85, 1994.
[Callaway92] T. Callaway and E. Swartzlander, Jr., Optimizing Arithmetic Elements for Signal Processing, VLSI Signal Processing V, pp. 91-100, IEEE Special Publications, 1992.
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Basics of Low Power Circuit and Logic Design

High Performance Processors

Basics of Low Power Circuit and Logic Design

Anantha Chandrakasan 1997

How to get 8 hours of operation ???

Anantha Chandrakasan 1997

Nominal Capacity (Watt-hours / lb)

(from Jon Eager, Gates Inc. , S. Watanabe, Sony Inc.)

Anantha Chandrakasan 1997

Where Does Power Go in CMOS?

Short-circuit or direct-path currents

Basics of Low Power Circuit and Logic Design

Anantha Chandrakasan 1997

Dynamic Power of a CMOS Gate

Basics of Low Power Circuit and Logic Design

Anantha Chandrakasan 1997

Modification for Circuits with Reduced Swing

Can exploit reduced swing to lower power

Anantha Chandrakasan 1997

Physical Capacitance of an Inverter

Important to account for capacitive non-linearities

Anantha Chandrakasan 1997

Node Capacitance is a Function of Voltage

Basics of Low Power Circuit and Logic Design

Anantha Chandrakasan 1997

Node Transition Activity and Power

Anantha Chandrakasan 1997

Factors Affecting Transition Activity, 0->1

Dynamic or timing dependent component

Basics of Low Power Circuit and Logic Design

Anantha Chandrakasan 1997

Type of Logic Function: NOR vs. XOR

Truth Table of a 2 input NOR gate

Basics of Low Power Circuit and Logic Design

Anantha Chandrakasan 1997

Type of Logic Function: NOR vs. XOR

Truth Table of a 2 input XOR gate

Basics of Low Power Circuit and Logic Design

Anantha Chandrakasan 1997

Type of Logic Style: Static vs. Dynamic

Power is only dissipated when Out=0!

Basics of Low Power Circuit and Logic Design

Anantha Chandrakasan 1997

Another Logic Style: Dynamic DCVSL

Guaranteed transition for every operation!

Basics of Low Power Circuit and Logic Design

Anantha Chandrakasan 1997

Influence of Signal Statistics on 0->1

0->1 is a strong function of signal statistics

Anantha Chandrakasan 1997

(a) Logic circuit without

(b) Logic circuit with

p0->1 = (1- pa pb) pa pb = 3/16

Need to use conditional probabilities to model

Anantha Chandrakasan 1997

Dynamic or Glitching Activity in CMOS

Sum Output Voltage, Volts

0->1 can be > 1 due to glitching!

Anantha Chandrakasan 1997

Glitch Reduction Using Balanced Paths

Basics of Low Power Circuit and Logic Design

Anantha Chandrakasan 1997

Comparison of Adder Topologies

Logic Transition Histogram