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A

ZZZ1

LA-6741P

DA60000JE10

Brazos PCM10 LA6741 Schematics Document


AMD APU Ontario-FT1+ FCH Hudson-M1

2010-11-30
3

REV:1.0

2010/05/06

Issued Date

Compal Electronics,Ltd.

Compal Secret Data

Security Classification

Title

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Cover Sheet
Size Document Number
Custom

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC

Date: Tuesday, November 30, 2010

Sheet
E

of

36

Compal Confidential
Model Name : Brazos
File Name : LA6741

DDR3-SO-DIMM X2

Single Channel

page 11

page 7,8

DDR3-800/1066(1.5V)
DDR3-800/1066(1.35V)

AMD FUSION APU


Ontario FT1
BGA-413

LVDS Conn.

BANK 0, 1, 2, 3

PCI-Express

page4~6

HDMI

LAN(10/100)

MINI Card

page 9

RTL8105E-VC-GR

WLAN
page 19

page 18

UMI*8

CRT

page 10

RJ45

page 18

Bluetooth

AMD HUDSON-M1
S-ATA

HDA Codec

605-BALL

Internal
clock GEN

CMOS Camera

page 18

3.3V 48MHz
page12~16

port 0

page 24

USB

3.3V 24.576MHz/48Mhz

ALC259-GR

USB conn x3

page 11

HD Audio

Card Reader

page 20
3

SPK
CONN

RTS5138

S-ATA HDD
Conn.page 17

page 17

LPC BUS

3 in 1
socket

page 21

RTC CKT.

EC

page 13

page 17

ENE KB926D3

Power/B
Power On/Off CKT.

page 22
page 23

page 24

USB I/O Conn.


DC/DC Interface CKT.

Int.KBD
Touch Pad

page 24

page 25
4

Power Circuit DC/DC

page 23

page 23

BIOS
Debug port
page 19

page 26,28,29
30,31,32,33

LED
page 27
A

2010/05/06

Issued Date

Compal Electronics,Ltd.

Compal Secret Data

Security Classification

CHARGER

page 23

Title

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

page 21
B

MB Block Diagram
Size Document Number
Custom

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC

Date:

Friday, November 26, 2010

Sheet
E

of

36

DDR3 Voltage Rails


FCH SM Bus0 address

+5VS

power
plane

+1.5VS
+CPU_CORE

+5VALW
+1.5V

+3VL
+5VL

S0

+3VALW

1010 0000

WLAN

A2

1010 0010

HEX

Address

EC SM Bus2 address

HEX

Address

Smart Battery

16H

0001 011X b

Device

HEX

APU internal themal sensor

Address
1001 100X b

+1.1VS

+1.1VALW

+1.0VS

S1

S3

DAC_SCL

SIC

SOURCE
TDP1_AUXP
TDP1_AUXN
LTDP0_AUXP
LTDP1_AUXN

DAC_SDA

SID
SVC
SVD
SMB_FCH_CK0
3

A0

SDDIM II

Device

S5 S4/AC & Battery


don't exist

SDDIM I

+0.75VS

S5 S4/ Battery only

Device

+1.8VS

S5 S4/AC

Address

EC SM Bus1 address

+NB_CORE

+RTCVCC

HEX

+3VS

+B

State

FCH SM Bus1 address

Device

Reserve

CONN@

ME CONNECTOR

8105E@

100M LAN function

SMB_FCH_DA0
SMB_FCH_CK1
SMB_FCH_DA1
SMB_EC_CK1
SMB_EC_DA1

8111E@

GLAN function

REAL@

ALC259-GR

VIA@

V1802T

ROM@

not support flash ROM

FROM@

Support flash ROM

SMB_EC_CK2
SMB_EC_DA2

POWER
PLAN

APU

+3VS

APU

+3VS

APU

+3VS

APU

+3VS

APU

+1.8VS

FCH

+3VS

FCH

+3VALW

EC

+5VALW

EC

+3VS

HDMI

LVDS

CRT

FCH

CPU
CORE

SDDIM
I/II

WLAN

BATT

APU

V
V
+5VS
V
+5VS
V
+3VALW
V
V

V
V
V

2009/05/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Title

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

MB Notes List
Size Document Number
Custom

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC

Date:

Friday, November 26, 2010

Sheet
E

of

36

POWER SEQUENCE

POWER MAP
+3VL
1

VIN

+5VL

B+
UP618CQAG

+3VL

+5VALW

+3VALW,+5VALW

SUSP#

+1.1VALW

+1.8VS
SY8033BDBC

ON/OFFBTN#

SUSP#
+5VS
SI4800BDY

EN_WOL#
+3V_LAN
AP2301GN

EC->FCH

EC_RSMRST#

EC->FCH

PBTN_OUT#

FCH->EC

FCH_SLP_S5#

EC->PWR

SYSON

NOTE1

T1>10ms, +3VALW to RSMRST#

T1

T2>100ms, RSMRST# to PBTN_OUT#

T2

T3>100ns, PBTN_OUT# to SLP_S5#

T3

T4>10ms, SLP_S5# to SYSON

T4

+1.5V

SUSP#
+3VS
SI4800BDY

ENVDD
2

+LCDVDD
SI4800BDY

POK

B+

+3VALW

FCH->EC

FCH_SLP_S3#

EC->PWR

SUSP#

+1.8VS
EC->PWR

1.1VSON#

+1.1VS_ON
+1.1VS

+1.1VS
IRF8113PBF

EC->PWR

SUSP#

PWR->EC

VR_ON
+CPU_CORE
+CPU_CORE_NB

FCH->APU

SYSON
3

+1.5V
RT8209BGQW

SUSP#

NOTE2

VGATE

T7>50ms, VGATE to EC_FCH_PWROK

T7

EC->FCH EC_FCH_PWROK
EC->FCH

T6>100ms, SUSP# to VR_ON

T6

VR_ON
+CPU_CORE
+CPU_CORE_NB

+1.0VS
STS11N3LLH5

ISL6265AH
RTZ

T5>10ms, SYSON to SUSP#

T5

+3VS,+5VS,+0.75VS

+1.1VALW

RT8209BGQW

The same with SLP_S5#

KB_RST#

FCH->DEVICE

A_RST#

FCH->APU

LDT_RST#

98ms>T7>150ms, EC_FCH_PWROK to APU_PWRGD

T8

APU_PWRGD

101ms>T7>113ms, EC_FCH_PWROK to A_RST#

T9

+1.5VS
SI4800BDY

NOTE1:

RSMRST# rise time(10% to 90%)<50ms


fail time<1ms

NOTE2:

EC_FCH_PWROK rise time(10% to 90%)<50ms


fail time<1ms

SUSP
+0.75VS
VDTT11V8

2010/05/06

Issued Date

Compal Electronics,Ltd.

Compal Secret Data

Security Classification

Title

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Powe map and sequence


Size Document Number
Custom

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC

Date:

Friday, November 26, 2010

Sheet
E

of

36

+1.8VS

2 1K_0402_5%

APU_SVD

2 300_0402_5%

LDT_RST#

R6

2 300_0402_5%

APU_PWRGD

R7

2 510_0402_1%

TEST_25_L

2 1K_0402_5%

TEST_36

R333 1

TDP1_TXP0
TDP1_TXN0

<10> HDMI_TX1+
<10> HDMI_TX1-

B9
A9

TDP1_TXP1
TDP1_TXN1

<10> HDMI_TX0+
<10> HDMI_TX0-

D10
C10

TDP1_TXP2
TDP1_TXN2

A10
B10

TDP1_TXP3
TDP1_TXN3

<12> LVDS_TX2+
<12> LVDS_TX2-

B5
A5

LTDP0_TXP0
LTDP0_TXN0

<12> LVDS_TX1+
<12> LVDS_TX1-

D6
C6

LTDP0_TXP1
LTDP0_TXN1

<12> LVDS_TX0+
<12> LVDS_TX0-

A6
B6

LTDP0_TXP2
LTDP0_TXN2

D8
C8

LTDP0_TXP3
LTDP0_TXN3

<10> HDMI_CLK+
<10> HDMI_CLK-

+3VS

R64

2 1K_0402_5%

APU_ALERT#_R

R14

2 1K_0402_5%

APU_PROCHOT

@R16
@
R16

2 1K_0402_5%

APU_SIC

@R17
@
R17

2 1K_0402_5%

R18

2 4.7K_0402_5%

<12> LVDS_CLK+
<12> LVDS_CLK-

APU_SID
HDMI_DAT

R19

2 4.7K_0402_5%

HDMI_SCL

R21

2 4.7K_0402_5%

LVDS_DAT

R22

2 4.7K_0402_5%

LVDS_SCL

<14> CLK_APU
<14> CLK_APU#

V2
V1

<14> CLK_APU_DP
<14> CLK_APU_DP#

D2
D1

DISP_CLKIN_H
DISP_CLKIN_L

<34>
<34>

APU_SIC
APU_SID
<14> LDT_RST#
<14> APU_PWRGD
<14> APU_PROCHOT_FCH#
<23> APU_PROCHOT_EC#

R23
R24
@R35
@
R35
R45

<13> APU_ALERT#

R26

1 1K_0402_5%

TEST_18

R27

1 1K_0402_5%

TEST_19

R28

2 510_0402_1%

@R29
@
R29

1 1K_0402_5%

R30
@R31
@
R31

2
2

1 1K_0402_5%

APU_SVC
APU_SVD

TEST_25_H
TEST_35

1 1K_0402_5% APU_LDT_STP#

SVC
SVD
SIC
SID

T3
T4

RESET_L
PWROK

U1
U2
T2

PROCHOT_L
THERMTRIP_L
ALERT_L

APU_TDI
APU_TDO
APU_TCLK
APU_TMS
APU_TRST#
DBRDY
DBREQ#

N2
N1
P1
P2
M4
M3
M1

TDI
TDO
TCK
TMS
TRST_L
DBRDY
DBREQ_L

F4
G1
F3

VDDCR_NB_SENSE
VDDCR_CPU_SENSE
VDDIO_MEM_S_SENSE

1 R271
1 R272
T28 PAD

<34> VDDCR_NB_SENSE_H
<34> VDDCR_APU_SENSE_H

TEST_15

J1
J2
P3
P4

1
2 LDT_RST#_R
1
2 APU_PWRGD_R
0_0402_5%
APU_PROCHOT
0_0402_5%
APU_THERMTRIP#_R
0_0402_5%1
2APU_ALERT#_R

0_0402_5%
0_0402_5%
1
2
1
2

R63

CLKIN_H
CLKIN_L

1 R273
1 R274

<34> VDDCR_NB_SENSE_L
<34> VDDCR_APU_SENSE_L

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

F1
B4
W11
V5

DP_ZVSS

H3

DP_BLON
DP_DIGON
DP_VARY_BL

G2
H2
H1

TDP1_AUXP
TDP1_AUXN

B2
C2

TDP1_HPD

C1

LTDP0_AUXP
LTDP0_AUXN

A3
B3

LTDP0_HPD

D3

DAC_RED
DAC_REDB
DAC_GREEN
DAC_GREENB
DAC_BLUE
DAC_BLUEB

C12
D13
A12
B12
A13
B13

R8

2 0.1U_0402_16V4Z

R5

2 51_0402_1%

TEST_33_L

2 0.1U_0402_16V4Z

R9

2 51_0402_1%

C2

2 150_0402_1%

ENBKL
ENVDD
INV_PWM

<12>
<12>
<12>

HDMI_SCL <10>
HDMI_DAT <10>

HDMI_HPD <10>
LVDS_SCL <12>
LVDS_DAT <12>
R10
R12

1 100K_0402_5%

2 150_0402_1%

R13

2 150_0402_1%

R15

2 150_0402_1%

+5VS

C3
CRT_R

<11>

CRT_G

<11>

CRT_B

<11>

E1
E2

DAC_SCL
DAC_SDA

F2
D4

DAC_ZVSS

D12

R20

TEST4
TEST5
TEST6
TEST14
TEST15
TEST16
TEST17
TEST18
TEST19
TEST25_H
TEST25_L
TEST28_H
TEST28_L
TEST31
TEST33_H
TEST33_L
TEST34_H
TEST34_L
TEST35
TEST36
TEST37

R1
R2
R6
T5
E4
K4
L1
L2
M2
K1
K2
L5
M5
M21
J18
J19
U15
T15
H4
N5
R5

TEST_4
TEST_5

PAD T1
PAD T2

TEST_14
TEST_15
TEST_16
TEST_17
TEST_18
TEST_19
TEST_25_H
TEST_25_L
TEST_28_H
TEST_28_L
TEST_31
TEST_33_H
TEST_33_L
TEST_34_H
TEST_34_L
TEST_35
TEST_36
TEST_37

PAD T4

U2
1
2
3
4

+VCC_FAN1
<23>

DAC_HSYNC
DAC_VSYNC

1A

10U_0805_10V4Z 1

EN_FAN1

CRT_HSYNC <11>
CRT_VSYNC <11>

C4

9
8
7
6
5

VEN Thermal Pad


VIN
GND
VO
GND
VSET
GND
GND

G996RD1U_TDFN8_3X3

CRT_DDC_CLK <11>
CRT_DDC_DATA <11>

10U_0805_6.3V6M

2 499_0402_1%

PAD T5
PAD T6

PAD T7
PAD T9
PAD T8

+3VS
@

PAD T10
PAD T11

R32
10K_0402_5%

JFAN

+VCC_FAN1

<23> FAN_SPEED1
VSS_SENSE
TEST38
DMAACTIVE_L

RSVD_1
RSVD_2
RSVD_3

K3
T1

1
APU_LDT_STP# <14>

C7
1000P_0402_50V7K

U1 1.5G@

U1 1.2G@

U1 1.0G@

1.6G

1.5G

1.2G

1.0G

1
2
3

1
2
3

4
5

GND
GND

CONN@

ACES_85205-03001

ONTARIO-2M161000-1.6G_BGA413

U1 1.6G@

1000P_0402_50V7K

40mil
PAD T13

C6
1

R4

A8
B8

TEST_33_H C1

R3

<10> HDMI_TX2+
<10> HDMI_TX2-

DP MISC

APU_SVC

VGA DAC

2 1K_0402_5%

TEST

DISPLAYPORT 1

R2

U1B

DISPLAYPORT 0

APU_LDT_STP#

CLK

TEST_35

2 1K_0402_5%

SER

1 1K_0402_5%

CTRL

R1

JTAG

R74

+3VS

2N7002DW-T/R7_SOT363-6
APU_SIC

@
1 R302

2 0_0402_5%

SCL3_LV

1 R364

2 0_0402_5%

EC_SMB_CK2 <23>

<15>

FCH

Q1B @
1 R366
2
0_0402_5%

EC

+3VS
+1.8VS

@
1 R363

2 0_0402_5%

SDA3_LV

1 R365

2 0_0402_5%

EC_SMB_DA2 <23>

<15>

HDT CONNECTOR
AMD APU DEBUG PORT

FCH

APU_SID

2N7002DW-T/R7_SOT363-6

+1.8VS

Q1A @

JP1 CONN@

EC

R33

APU_TCLK

R34

1 1K_0402_5%

1K_0402_5%

APU_TMS

R36

1 1K_0402_5%

APU_TDI

R37

1 1K_0402_5%

APU_TDO

R42

2 300_0402_5%

R43

2 0_0402_5%

TEST_19

J108_PLLTST1 R44

2 0_0402_5%

TEST_18

1 R367
2
0_0402_5%

APU_TRST#

0_0402_5%
R38 1
2

+3VS
R39

R40
R41

APU_TRST#_R

10K_0402_5%
10K_0402_5%
10K_0402_5%

R70
10K_0402_5%

10

10

11

12

12

13

13

14

14

DBRDY
DBREQ#

15

15

16

16

17

17

18

18

19

19

20

20

LDT_RST#

J108_PLLTST0

+1.8VS

2 2

R25
1K_0402_5%

APU_PWRGD

9
11

SAMTE_ASP-136446-07-B
E

APU_THERMTRIP#_R

APU_THERMTRIP# <15>

Q212
MMBT3904_NL_SOT23-3

1 R368
@

2 0_0402_5%

Issued Date

2009/05/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Title

DISPLAY,CLK,JTAG
Size Document Number
Custom

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC

Date:

Friday, December 03, 2010

Sheet
1

of

36

<8,9>
<8,9>
<8,9>
<8,9>
<8,9>

DDR_D[0..63]
DDR_DM[0..7]
DDR_DQS#[0..7]
DDR_DQS[0..7]
DDR_MA[0..15]

U1E

DDR_DQS0
DDR_DQS#0
DDR_DQS1
DDR_DQS#1
DDR_DQS2
DDR_DQS#2
DDR_DQS3
DDR_DQS#3
DDR_DQS4
DDR_DQS#4
DDR_DQS5
DDR_DQS#5
DDR_DQS6
DDR_DQS#6
DDR_DQS7
DDR_DQS#7

A16
B16
B20
A20
E23
E22
J22
J23
R22
P22
W22
V22
AC20
AC21
AB16
AC16

M_DQS_H0
M_DQS_L0
M_DQS_H1
M_DQS_L1
M_DQS_H2
M_DQS_L2
M_DQS_H3
M_DQS_L3
M_DQS_H4
M_DQS_L4
M_DQS_H5
M_DQS_L5
M_DQS_H6
M_DQS_L6
M_DQS_H7
M_DQS_L7

M17
M16
M19
M18
N18
N19
L18
L17

M_CLK_H0
M_CLK_L0
M_CLK_H1
M_CLK_L1
M_CLK_H2
M_CLK_L2
M_CLK_H3
M_CLK_L3

<8,9> DDR_RST#
<8,9> DDR_EVENT#

L23
N17

M_RESET_L
M_EVENT_L

<8,9> DDR_CKE0
<8,9> DDR_CKE1

F15
E15

M_CKE0
M_CKE1

<8> DDR_A_CLK0
<8> DDR_A_CLK0#
<8> DDR_A_CLK1
<8> DDR_A_CLK1#
<9> DDR_B_CLK0
<9> DDR_B_CLK0#
<9> DDR_B_CLK1
<9> DDR_B_CLK1#

<8>
<8>
<9>
<9>

DDR_A_ODT0
DDR_A_ODT1
DDR_B_ODT0
DDR_B_ODT1

W19
V15
U19
W15

M0_ODT0
M0_ODT1
M1_ODT0
M1_ODT1

<8>
<8>
<9>
<9>

DDR_A_CS0#
DDR_A_CS1#
DDR_B_CS0#
DDR_B_CS1#

T17
W16
U17
V16

M0_CS_L0
M0_CS_L1
M1_CS_L0
M1_CS_L1

U18
V19
V17

M_RAS_L
M_CAS_L
M_WE_L

<8,9> DDR_RAS#
<8,9> DDR_CAS#
<8,9> DDR_WE#

DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7

M_DATA8
M_DATA9
M_DATA10
M_DATA11
M_DATA12
M_DATA13
M_DATA14
M_DATA15

C18
A19
B21
D20
A18
B18
A21
C20

DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15

M_DATA16
M_DATA17
M_DATA18
M_DATA19
M_DATA20
M_DATA21
M_DATA22
M_DATA23

C23
D23
F23
F22
C22
D22
F20
F21

DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23

M_DATA24
M_DATA25
M_DATA26
M_DATA27
M_DATA28
M_DATA29
M_DATA30
M_DATA31

H21
H23
K22
K21
G23
H20
K20
K23

DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31

M_DATA32
M_DATA33
M_DATA34
M_DATA35
M_DATA36
M_DATA37
M_DATA38
M_DATA39

N23
P21
T20
T23
M20
P20
R23
T22

DDR_D32
DDR_D33
DDR_D34
DDR_D35
DDR_D36
DDR_D37
DDR_D38
DDR_D39

M_DATA40
M_DATA41
M_DATA42
M_DATA43
M_DATA44
M_DATA45
M_DATA46
M_DATA47

V20
V21
Y23
Y22
T21
U23
W23
Y21

DDR_D40
DDR_D41
DDR_D42
DDR_D43
DDR_D44
DDR_D45
DDR_D46
DDR_D47

M_DATA48
M_DATA49
M_DATA50
M_DATA51
M_DATA52
M_DATA53
M_DATA54
M_DATA55

Y20
AB22
AC19
AA18
AA23
AA20
AB19
Y18

DDR_D48
DDR_D49
DDR_D50
DDR_D51
DDR_D52
DDR_D53
DDR_D54
DDR_D55

M_DATA56
M_DATA57
M_DATA58
M_DATA59
M_DATA60
M_DATA61
M_DATA62
M_DATA63

AC17
Y16
AB14
AC14
AC18
AB18
AB15
AC15

DDR_D56
DDR_D57
DDR_D58
DDR_D59
DDR_D60
DDR_D61
DDR_D62
DDR_D63

M_VREF

M23

M_ZVDDIO_MEM_S

M22

<14> UMI_C_TXP[0..3]
<14> UMI_C_TXN[0..3]

<14> UMI_C_RXP[0..3]
<14> UMI_C_RXN[0..3]

U1A

LAN

AA6
Y6

P_GPP_RXP0
P_GPP_RXN0

AB4
AC4

P_GPP_RXP1
P_GPP_RXN1

<19> PCIE_PTX_C_IRX_P2
<19> PCIE_PTX_C_IRX_N2

AA1
AA2

P_GPP_RXP2
P_GPP_RXN2

<20> PCIE_PTX_C_IRX_P3
PCIE_PTX_C_IRX_N3

Y4
Y3

P_GPP_RXP3
P_GPP_RXN3

WLAN <20>

+1.0VS

R46

2 2K_0402_1% Y14

UMI_C_RXP0
UMI_C_RXN0

AA12
Y12

UMI_C_RXP1
UMI_C_RXN1

AA10
Y10

UMI_C_RXP2
UMI_C_RXN2

AB10
AC10

UMI_C_RXP3
UMI_C_RXN3

AC7
AB7

PCIE I/F

M_DM0
M_DM1
M_DM2
M_DM3
M_DM4
M_DM5
M_DM6
M_DM7

B14
A15
A17
D18
A14
C14
C16
D16

P_GPP_TXP0
P_GPP_TXN0

AB6
AC6

P_GPP_TXP1
P_GPP_TXN1

AB3
AC3

P_GPP_TXP2
P_GPP_TXN2

Y1
Y2

PCIE_ITX_PRX_P2 C338 1
PCIE_ITX_PRX_N2 C339 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

PCIE_ITX_C_PRX_P2 <19>
PCIE_ITX_C_PRX_N2 <19>

LAN

P_GPP_TXP3
P_GPP_TXN3

V3
V4

PCIE_ITX_PRX_P3 C340 1
PCIE_ITX_PRX_N3 C341 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

PCIE_ITX_C_PRX_P3 <20>
PCIE_ITX_C_PRX_N3 <20>

WLAN

P_ZVDD_10

P_ZVSS

P_UMI_RXP0
P_UMI_RXN0

UMI I/F

D15
B19
D21
H22
P23
V23
AB20
AA16

M_DATA0
M_DATA1
M_DATA2
M_DATA3
M_DATA4
M_DATA5
M_DATA6
M_DATA7

P_UMI_RXP1
P_UMI_RXN1
P_UMI_RXP2
P_UMI_RXN2
P_UMI_RXP3
P_UMI_RXN3

AA14 R47

2 1.27K_0402_1%

P_UMI_TXP0
P_UMI_TXN0

AB12
AC12

UMI_TXP0 C9
UMI_TXN0 C10

1
1

2 0.1U_0402_16V7K UMI_C_TXP0
2 0.1U_0402_16V7K UMI_C_TXN0

P_UMI_TXP1
P_UMI_TXN1

AC11
AB11

UMI_TXP1 C11
UMI_TXN1 C12

1
1

2 0.1U_0402_16V7K UMI_C_TXP1
2 0.1U_0402_16V7K UMI_C_TXN1

P_UMI_TXP2
P_UMI_TXN2

AA8
Y8

UMI_TXP2 C13
UMI_TXN2 C14

1
1

2 0.1U_0402_16V7K UMI_C_TXP2
2 0.1U_0402_16V7K UMI_C_TXN2

P_UMI_TXP3
P_UMI_TXN3

AB8
AC8

UMI_TXP3 C15
UMI_TXN3 C16

1
1

2 0.1U_0402_16V7K UMI_C_TXP3
2 0.1U_0402_16V7K UMI_C_TXN3

ONTARIO-2M161000-1.6G_BGA413

+1.5V

+M_VREF

+1.5V

M_BANK0
M_BANK1
M_BANK2

DDR_DM0
DDR_DM1
DDR_DM2
DDR_DM3
DDR_DM4
DDR_DM5
DDR_DM6
DDR_DM7

R18
T18
F16

DDR SYSTEM MEMORY

<8,9> DDR_BS0
<8,9> DDR_BS1
<8,9> DDR_BS2

M_ADD0
M_ADD1
M_ADD2
M_ADD3
M_ADD4
M_ADD5
M_ADD6
M_ADD7
M_ADD8
M_ADD9
M_ADD10
M_ADD11
M_ADD12
M_ADD13
M_ADD14
M_ADD15

R48
R49

39.2_0402_1%

1K_0402_1%
+M_VREF 1000P_0402_50V7K
1
1
C428
C172

ONTARIO-2M161000-1.6G_BGA413

R17
H19
J17
H18
H17
G17
H15
G18
F19
E19
T19
F17
E18
W17
E16
G15

DDR_MA0
DDR_MA1
DDR_MA2
DDR_MA3
DDR_MA4
DDR_MA5
DDR_MA6
DDR_MA7
DDR_MA8
DDR_MA9
DDR_MA10
DDR_MA11
DDR_MA12
DDR_MA13
DDR_MA14
DDR_MA15

R50

1K_0402_1%

0.1U_0402_16V4Z
+1.5V

DDR_EVENT# R51

1 1K_0402_1%

DDR_RST#

1 1K_0402_1%

R69
@

2010/05/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Title

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

DDRIII,UMI
Size Document Number
Custom

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC

Date:

Friday, December 03, 2010

Sheet
1

of

36

+CPU_CORE

C19

C21

1
1U_0402_6.3V4Z

@
C939 2

2
2
0.1U_0402_16V4Z

2
1U_0402_6.3V4Z

2
10U_0805_6.3V6M

150mA

VDD_18_DAC

W9

180P_0402_50V8J
C938
@

1U_0402_6.3V4Z
1
C28
C27

POWER

L2

220
_3A
DCR:0.04

@ C23

+1.8VS

1
+

FBMA-L11-201209-221LMA30T_0805
10U_0805_6.3V6M

+1.0VS_VDDPL

200mA

PCIE/IO/DDR3 Phy

VDD_10_1
VDD_10_2
VDD_10_3
VDD_10_4

U13
W13
V12
T12

5500mA0.1U_0402_16V4Z
1

C52

C937
@
180P_0402_50V8J 2

C53

C22
330U_2.5V_M

10U_0805_6.3V6M

10U_0805_6.3V6M

C29

C30

ESR:17ohm(MAX)

C31

L3

C50

+1.0VS

1U_0402_6.3V4Z

C40

C41

C42

+1.0VS_VDD

C51

10U_0805_6.3V6M
C48

120
_5A +1.0VS
DCR:0.02

C43

GND

VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSSBG_DAC

C46

0.1U_0402_16V4Z

C47

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

L4 1
2
FBMA-L11-201209-121LMA50

C49

+CPU_CORE_NB

2
2
2
2
0.1U_0402_16V4Z
1U_0402_6.3V4Z

2
+CPU_CORE_NB

+3VS

C54

0.1U_0402_16V4Z

C45

1U_0402_6.3V4Z

+1.0VS

N13
N20
N22
P10
P14
R4
R7
R20
T6
T9
T11
T13
U4
U5
U7
U12
U20
U22
V8
V9
V11
V13
W1
W2
W4
W5
W7
W12
W20
Y5
Y7
Y9
Y11
Y13
Y15
Y17
Y19
AA4
AA22
AB2
AB5
AB9
AB13
AB17
AB21
AC5
AC9
AC13
A11

C55

1
C56 +

2
2

1
@
C57 +
2

1
+

C64
@

220U_D2_4VM_R15 2

10U_0805_6.3V6M

C60

1U_0402_6.3V4Z

C61

C62

10U_0805_6.3V6M

+CPU_CORE_NB

10U_0805_6.3V6M

C59

C932
@

+CPU_CORE_NB

C58

10U_0805_6.3V6M

1
C931
@

10U_0805_6.3V6M

ESR:9ohm(MAX)

C63

10U_0805_6.3V6M

1U_0402_6.3V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z
C65

C66

C67

C68

C69

C70

C71

C72

C73

0.1U_0402_16V4Z
1U_0402_6.3V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

+1.5V

+1.5V

ESR:9ohm(MAX)
330U_D2_2.5VY_R9M

C75

C74 +

@
10U_0805_6.3V6M

1
C933
@

C934
@

180P_0402_50V8J

C44

1U_0402_6.3V4Z

A4

C167
0.1U_0402_16V4Z

10U_0805_6.3V6M

180P_0402_50V8J

DP Phy/IO

VDD_33

2
10U_0805_6.3V6M

1U_0402_6.3V4Z

ESR:9ohm(MAX)
500mA

C35

10U_0805_6.3V6M

0.1U_0402_16V4Z

C34

+CPU_CORE

C39

C33

10U_0805_6.3V6M

C32

FBMA-L11-201209-221LMA30T_0805

1U_0402_6.3V4Z

220
_3A
DCR:0.04

10U_0805_6.3V6M

10U_0805_6.3V6M

+1.5V
1U_0402_6.3V4Z

1U_0402_6.3V4Z

10U_0805_6.3V6M 1U_0402_6.3V4Z

2
1
C76

C78

0.1U_0402_16V4Z
C79

C80

C81

C82

C83

C84

1
A

C77

10U_0805_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

2010/05/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

ONTARIO-2M161000-1.6G_BGA413

+CPU_CORE

180P_0402_50V8J

DIS PLL

VDDPL_10

1U_0402_6.3V4Z
U11 180P_0402_50V8J
1
1
1
C38
C37
C936
C36
@
2
2
2
0.1U_0402_16V4Z

DDR3

1
C26 +

+1.8VS

U1D

10U_0805_6.3V6M

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49

C930
@

1
C25 +

ESR:9ohm(MAX)

ONTARIO-2M161000-1.6G_BGA413

A7
B7
B11
B17
B22
C4
D5
D7
D9
D11
D14
B15
D17
D19
E7
E9
E12
E20
F8
F11
F13
G4
G5
G7
G9
G12
G20
G22
H6
H11
H13
J4
J5
J7
J20
K10
K14
L4
L6
L8
L11
L13
L20
L22
M7
N4
N6
N8
N11

C929
@

C24 +

330U_D2_2.5VY_R9M

VDDIO_MEM_S_1
VDDIO_MEM_S_2
VDDIO_MEM_S_3
VDDIO_MEM_S_4
VDDIO_MEM_S_5
VDDIO_MEM_S_6
VDDIO_MEM_S_7
VDDIO_MEM_S_8
VDDIO_MEM_S_9
VDDIO_MEM_S_10
VDDIO_MEM_S_11

C18

330U_D2_2.5VY_R9M

G16
G19
E17
J16
L16
L19
N16
R16
R19
W18
U16

C17

10U_0805_6.3V6M

VDDCR_NB_1
VDDCR_NB_2
VDDCR_NB_3
VDDCR_NB_4
VDDCR_NB_5
VDDCR_NB_6
VDDCR_NB_7
VDDCR_NB_8
VDDCR_NB_9
VDDCR_NB_10
VDDCR_NB_11
VDDCR_NB_12
VDDCR_NB_13
VDDCR_NB_14
VDDCR_NB_15
VDDCR_NB_16
VDDCR_NB_17
VDDCR_NB_18
VDDCR_NB_19
VDDCR_NB_20
VDDCR_NB_21
VDDCR_NB_22

330U_D2_2.5VY_R9M

C20

1
1

330U_D2_2.5VY_R9M

+1.8VS

L1 1
2
FBMA-L11-201209-121LMA50

180P_0402_50V8J

C426

1U_0402_6.3V4Z

180P_0402_50V8J

DAC

2000mA

E8
E11
E13
F9
F12
G11
G13
H9
H12
K11
K13
L10
L12
L14
M11
M12
M13
N10
N12
N14
P11
P13

GPU AND NB CORE

+1.5V

1U_0402_6.3V4Z

+1.8VS_DAC

10000mA

VDD_18_1
VDD_18_2
VDD_18_3
VDD_18_4
VDD_18_5
VDD_18_6
VDD_18_7

180P_0402_50V8J

330U_D2_2.5VY_R9M

+CPU_CORE_NB

TSense/PLL/DP/PCIE/IO

VDDCR_CPU_1
VDDCR_CPU_2
VDDCR_CPU_3
VDDCR_CPU_4
VDDCR_CPU_5
VDDCR_CPU_6
VDDCR_CPU_7
VDDCR_CPU_8
VDDCR_CPU_9
VDDCR_CPU_10
VDDCR_CPU_11
VDDCR_CPU_12
VDDCR_CPU_13
VDDCR_CPU_14
VDDCR_CPU_15

U8
W8
U6
U9
W6
T7
V7

120
_5A
DCR:0.02

+1.8VS_VDD

2000mA

CPU CORE

E5
E6
F5
F7
G6
G8
H5
H7
J6
J8
L7
M6
M8
N7
R8

180P_0402_50V8J

U1C

11000mA

330U_D2_2.5VY_R9M

+CPU_CORE
+CPU_CORE

Title

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

PWR,BYPASS
Size Document Number
Custom

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC

Date:

Friday, November 26, 2010

Sheet
1

of

36

+1.5V

+1.5V

<6,9> DDR_DQS#[0..7]

JDDR1

+1.5V

+V_DDR3_DIMM_REF

<6,9> DDR_D[0..63]

R52

<6,9> DDR_DM[0..7]
+V_DDR3_DIMM_REF

R53

C86
1000P_0402_50V7K

<6,9> DDR_DQS[0..7]

1K_0402_1%

+VREF_DQA

2 0_0402_5%

C85

DDR_D0
DDR_D1

1 0.1U_0402_16V4Z

DDR_DM0

<6,9> DDR_MA[0..15]

R54

DDR_D8
DDR_D9

+V_DDR3_DIMM_REF

DDR_D2
DDR_D3

DDR_DQS#1
DDR_DQS1

1K_0402_1%

DDR_D10
DDR_D11

Put it between DDR3 +1.5VS shape and GND shape

DDR_D16
DDR_D17

+1.5V
0.1U_0402_16V4Z

DDR_DQS#2
DDR_DQS2

1
C330
@

1
C113
@

1
C293 @
0.01U_0402_16V7K

1
C328 @
0.01U_0402_16V7K

DDR_D18
DDR_D19

C329 @
0.01U_0402_16V7K

DDR_D24
DDR_D25
DDR_DM3

0.1U_0402_16V4Z
DDR_D26
DDR_D27

Layout Note:
Place near JDDR1
<6,9> DDR_CKE0

Layout Note: Place these 4 Caps near Command


and Control signals of DIMMA

change two 100U to one 220U


06/21

+1.5V

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

<6,9> DDR_BS2
DDR_MA12
DDR_MA9

10U_0603_6.3V6M
DDR_MA8
DDR_MA5

1
1

C92

C91

C94

C93

C96

C95

1
C97

1
C98

1
C99

1
C100

1
C101

C102

+ C87
@
220U_D2_4VM_R15

DDR_MA3
DDR_MA1

<6> DDR_A_CLK0
<6> DDR_A_CLK0#
DDR_MA10

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0603_6.3V6M

<6,9> DDR_BS0
<6,9> DDR_WE#
<6,9> DDR_CAS#
DDR_MA13
<6> DDR_A_CS1#

Layout Note:
Place near JDDR1.203 & JDDR1.204

DDR_D32
DDR_D33
DDR_DQS#4
DDR_DQS4

+0.75VS
1U_0402_6.3V6K

1U_0402_6.3V6K

DDR_D34
DDR_D35

10U_0805_6.3V6M

C106

C107

C108

C109

DDR_D40
DDR_D41
C110
DDR_DM5

C105

1U_0402_6.3V6K

1U_0402_6.3V6K

DDR_D42
DDR_D43
DDR_D48
DDR_D49

10U_0805_6.3V6M

DDR_DQS#6
DDR_DQS6
DDR_D50
DDR_D51
DDR_D56
DDR_D57
DDR_DM7
DDR_D58
DDR_D59
R56

2 10K_0402_5%

C103
2.2U_0603_6.3V6K

C104
0.1U_0402_16V4Z

R57
10K_0402_5%

VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT

205
207

GND1
BOSS1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

BOSS2

206
208

5.2mmGND2

2010/05/06

DDR_DQS#0
DDR_DQS0
DDR_D6
DDR_D7
DDR_D12
DDR_D13
D

DDR_DM1
DDR_RST# <6,9>
DDR_D14
DDR_D15
DDR_D20
DDR_D21
DDR_DM2
DDR_D22
DDR_D23
DDR_D28
DDR_D29
DDR_DQS#3
DDR_DQS3

Need close to JDDR1


@
C264

DDR_D30
DDR_D31

DDR_CKE1

33P_0402_50V8J

DDR_CKE1 <6,9>
DDR_MA15
DDR_MA14
C

DDR_MA11
DDR_MA7
DDR_MA6
DDR_MA4
DDR_MA2
DDR_MA0
DDR_A_CLK1 <6>
DDR_A_CLK1# <6>
DDR_BS1 <6,9>
DDR_RAS# <6,9>
DDR_A_CS0# <6>
DDR_A_ODT0 <6>
+V_DDR3_DIMM_REF

DDR_A_ODT1 <6>
+DDR_VREF_CA_DIMMA

R55

DDR_D36
DDR_D37

2 0_0402_5%

C89
1000P_0402_50V7K

DDR_DM4

C90
0.1U_0402_16V4Z

DDR_D38
DDR_D39
DDR_D44
DDR_D45

DDR_DQS#5
DDR_DQS5
DDR_D46
DDR_D47
DDR_D52
DDR_D53
DDR_DM6
DDR_D54
DDR_D55
DDR_D60
DDR_D61
DDR_DQS#7
DDR_DQS7
DDR_D62
DDR_D63

+0.75VS

DDR_EVENT# <6,9>
SMB_FCH_DA0 <9,15>
SMB_FCH_CK0 <9,15>

DDR3 SO-DIMM A
Standard Type

Compal Electronics, Inc.


2010/02/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

DDR_D4
DDR_D5

Compal Secret Data

Security Classification

Issued Date

VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS

LCN_DAN06-K4526-0102

+3VS

CONN@

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

Title

DDRIII-SODIMM A
Size Document Number
Custom

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC

Date:

Friday, December 03, 2010

Sheet
1

of

36

+1.5V

+1.5V
JDDR2

R58

+V_DDR3_DIMM_REF

VREF_DQB

2 0_0402_5%

C111
1000P_0402_50V7K
<6,8> DDR_DQS#[0..7]

C112

1 0.1U_0402_16V4Z

DDR_DM0

DDR_D2
DDR_D3

<6,8> DDR_D[0..63]
D

DDR_D0
DDR_D1

DDR_D8
DDR_D9

<6,8> DDR_DM[0..7]

DDR_DQS#1
DDR_DQS1

<6,8> DDR_DQS[0..7]
<6,8> DDR_MA[0..15]

DDR_D10
DDR_D11
DDR_D16
DDR_D17
DDR_DQS#2
DDR_DQS2
DDR_D18
DDR_D19
DDR_D24
DDR_D25
DDR_DM3
Need close to JDDR2
@
1

Layout Note:
Place near JP3

DDR_D26
DDR_D27

C288

DDR_CKE0

10U_0603_6.3V6M

<6,8> DDR_CKE0

change two 100U to one 220U


06/21

+1.5V
10U_0603_6.3V6M

10U_0603_6.3V6M
0.1U_0402_16V4Z

0.1U_0402_16V4Z

<6,8> DDR_BS2
DDR_MA12
DDR_MA9

10U_0603_6.3V6M

DDR_MA8
DDR_MA5

1
1

C118

C117

1
C119

1
C120

1
C121

C123

C124

C125

C126

C122

1
C127

+ C114
DDR_MA3
DDR_MA1

C128

220U_D2_4VM_R15
<6> DDR_B_CLK0
<6> DDR_B_CLK0#

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_MA10

10U_0603_6.3V6M
<6,8> DDR_BS0
<6,8> DDR_WE#
<6,8> DDR_CAS#

DDR_MA13

Layout Note:
Place near JP3.203 & JP3.204

<6> DDR_B_CS1#

DDR_D32
DDR_D33

+0.75VS
1U_0402_6.3V6K

DDR_DQS#4
DDR_DQS4

1U_0402_6.3V6K

DDR_D34
DDR_D35
B

C129

C130

C131

C132

DDR_D40
DDR_D41

C133
10U_0805_6.3V6M

DDR_DM5
DDR_D42
DDR_D43

1U_0402_6.3V6K

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

205

G1

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

1U_0402_6.3V6K
DDR_D48
DDR_D49
DDR_DQS#6
DDR_DQS6
DDR_D50
DDR_D51
DDR_D56
DDR_D57
DDR_DM7
SA0

DDR_D58
DDR_D59

SA1
@
R139 1

Compal
common design
ADM CRB

0
1

2 10K_0402_5%
R60 1

+3VS

0
C134
2.2U_0603_6.3V6K

1
R61 @
1
R203

2 0.1U_0402_16V4Z

C135

DDR_DQS#0
DDR_DQS0
DDR_D6
DDR_D7
DDR_D12
DDR_D13

DDR_DM1
DDR_RST# <6,8>
DDR_D14
DDR_D15
DDR_D20
DDR_D21
DDR_DM2
DDR_D22
DDR_D23
DDR_D28
DDR_D29
DDR_DQS#3
DDR_DQS3
DDR_D30
DDR_D31

2010/05/06

Issued Date

2 10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

G2

206

5.2mm

DDR_MA11
DDR_MA7
DDR_MA6
DDR_MA4
DDR_MA2
DDR_MA0
DDR_B_CLK1 <6>
DDR_B_CLK1# <6>
DDR_BS1 <6,8>
DDR_RAS# <6,8>
DDR_B_CS0# <6>
DDR_B_ODT0 <6>
DDR_B_ODT1 <6>
DDR_VREF_CA_DIMMB R59
DDR_D36
DDR_D37

+V_DDR3_DIMM_REF

2 0_0402_5%

C115
1000P_0402_50V7K

DDR_DM4

C116
0.1U_0402_16V4Z

DDR_D38
DDR_D39
B

DDR_D44
DDR_D45
DDR_DQS#5
DDR_DQS5
DDR_D46
DDR_D47
DDR_D52
DDR_D53
DDR_DM6
DDR_D54
DDR_D55
DDR_D60
DDR_D61
DDR_DQS#7
DDR_DQS7
DDR_D62
DDR_D63

+0.75VS

DDR_EVENT# <6,8>
SMB_FCH_DA0 <8,15>
SMB_FCH_CK0 <8,15>

DDR3 SO-DIMM B
REV Type

LCN_DAN06-K4526-0101

Compal Electronics, Inc.


Title

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

DDR_CKE1 <6,8>
DDR_MA15
DDR_MA14

Compal Secret Data

Security Classification

DDR_D4
DDR_D5

33P_0402_50V8J

Layout Note: Place these 4 Caps near Command


and Control signals of DIMMA
C

CONN@

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

DDRIII-SODIMM B
Size

Document Number

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC


Date:

Friday, December 03, 2010

Sheet
1

of

36

<5> HDMI_TX2+
<5> HDMI_TX2<5> HDMI_TX1+
<5> HDMI_TX1<5> HDMI_TX0+
<5> HDMI_TX0-

C136 1
C137 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

HDMI_CLKHDMI_CLK+

HDMI_C_CLKHDMI_C_CLK+

HDMI_TX2+
HDMI_TX2-

C138 1
C139 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

HDMI_C_TX2+
HDMI_C_TX2-

HDMI_TX1+
HDMI_TX1-

C140 1
C141 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

HDMI_C_TX1+
HDMI_C_TX1-

HDMI_TX0+
HDMI_TX0-

C142 1
C143 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

HDMI_C_TX0+
HDMI_C_TX0-

0_0402_5%
D

2N7002DW-T/R7_SOT363-6

<5> HDMI_DAT

HDMIDAT_R

6
Q2A

1
R91 @
0_0402_5%

<5> HDMI_CLK<5> HDMI_CLK+

2 R62

+3VS

<5> HDMI_SCL

HDMICLK_R

Q2B
2N7002DW-T/R7_SOT363-6
2

1
R93 @
0_0402_5%

L5

HDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_DET

+5VS
+3VS

L6

HDMI_TX0-_CONN

A
3

L7

100K_0402_5%
R1192
@

C166 @
0.1U_0402_16V4Z

HDMI_HPD <5>

U7 @
74AHCT1G125GW_SOT353-5

100K_0402_5%
R119

HDMI_TX1+_CONN

+5VS

HDMI_C_TX1- 1

WCM-2012-670T

HDMI_C_TX1+ 4

R84 @
2.2K_0402_5%

HDMI_TX1-_CONN

C165 @
0.1U_0402_16V4Z

R98

1
5

HDMI_TX0+_CONN

HDMI_C_TX0- 1

HDMI_C_TX0+ 4

OE#

0_0402_5%
1

WCM-2012-670T

HDMI_C_CLK- 1

HDMI_C_CLK+ 4

WCM-2012-670T
D11 @

HDMI_TX2+_CONN

HDMI_C_TX2- 1

HDMI_TX2-_CONN

BAT54S-7-F_SOT23-3

L8
HDMI_C_TX2+ 4

HDMI_DET
+5VS

WCM-2012-670T

2
2
2
2
2
2
2
2

HDMI_CLK+_CONN
HDMI_CLK-_CONN
HDMI_TX0+_CONN
HDMI_TX0-_CONN
HDMI_TX1+_CONN
HDMI_TX1-_CONN
HDMI_TX2+_CONN
HDMI_TX2-_CONN

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

+5VS_HDMI
R78
2.2K_0402_5%
HDMIDAT_R
HDMICLK_R

R81
HDMI_TX0+_CONN
R82
HDMI_TX0-_CONN
R83
HDMI_TX1+_CONN
R85
HDMI_TX1-_CONN
R87
HDMI_TX2+_CONN
R89
HDMI_TX2-_CONN
R92

NEAR CONNECT

499_0402_1%

+5VS_HDMI 1

2 470_0402_1%

@R1560
@
R1560

2 470_0402_1%

@R1561
@
R1561

2 470_0402_1%

@R1562
@
R1562

2 470_0402_1%

JHDMI

HDMI_DET 19
18
17
16
15
14
13
HDMI_CLK-_CONN
12
11
HDMI_CLK+_CONN
10
HDMI_TX0-_CONN
9
8
HDMI_TX0+_CONN
7
HDMI_TX1-_CONN
6
5
HDMI_TX1+_CONN
4
HDMI_TX2-_CONN
3
2
HDMI_TX2+_CONN
1

499_0402_1%
499_0402_1%

CONN@

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

20
21
22
23

SUYIN_100042GR019M23DZL

499_0402_1%
499_0402_1%

C144
0.1U_0402_16V4Z
B

499_0402_1%

2
G
S

0_0402_5%
2 R90
1
2
1
R88
0_0402_5%

+3VS
+5VS

Q10

499_0402_1%
2N7002W-T/R7_SOT323-3
A

2010/05/06

Issued Date

Compal Electronics,Ltd.

Compal Secret Data

Security Classification

2010/02/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

R79
2.2K_0402_5%

@R1559
@
R1559

499_0402_1%

R80
HDMI_CLK-_CONN

HDMI_CLK+_CONN

F1
1.1A_6VDC_FUSE

1
1
1
1
1
1
1
1

R65
R66
R67
R68
R71
R72
R73
R75

@
@
@
@
@
@
@
@

HDMI_C_CLK+
HDMI_C_CLKHDMI_C_TX0+
HDMI_C_TX0HDMI_C_TX1+
HDMI_C_TX1HDMI_C_TX2+
HDMI_C_TX2-

D5
3 PMEG2010ET SOT23
+VCC_HDMI
1
2

Title

HDMI Conn
Size Document Number
Custom

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC

Date: Friday, December 03, 2010

Sheet
1

10

of

36

CRT Connector

+CRT_VCC

D7
D8
D9
@
@
@
DAN217_SC59 DAN217_SC59 DAN217_SC59

+5VS

+R_CRT_VCC
D10

F2

W=40mils

W=40mils

1.1A_6VDC_FUSE

PMEG2010ET SOT23

+3VS

2
CRT_R_2

<5>

CRT_G

L14 1
2
FBMA-L10-160808-600LMT_2P

CRT_G_2

<5>

CRT_B

L12 1
2
FBMA-L10-160808-600LMT_2P

CRT_B_2

1
2

5P_0402_50V8C

C146 1

1
C151
2

C147 1

5P_0402_50V8C

1
C150

5P_0402_50V8C

C149 1

R96

5P_0402_50V8C

5P_0402_50V8C

5P_0402_50V8C

R95

150_0402_1%

150_0402_1%

150_0402_1%

R94

L11 1
2
FBMA-L10-160808-600LMT_2P

CRT_R

<5>

JCRT CONN@

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

C148 1

U4
CRT_HSYNC_0

R99

<5> CRT_HSYNC

C152

OE#

2
0.1U_0402_16V4Z

1 10K_0402_5%

2 CRT_HSYNC_1
27_0402_5%

C155
10P_0402_50V8J

74AHCT1G125GW_SOT353-5

C156
10P_0402_50V8J

2
0.1U_0402_16V4Z

U5

CRT_VSYNC_0
R100

<5> CRT_VSYNC

OE#

1
C158

68P_0402_50V8K

+CRT_VCC

100P_0402_50V8J

1
C153

NEED CHECK SYMBOL


06/02

G
G

16
17

SUYIN_070546FR015S297ZR

+CRT_VCC
R97

C145
0.1U_0402_16V4Z

CRT_VSYNC_1
27_0402_5%

C154

DAT_R R254 1

2 33_0402_5%

DAT

CLK_R

2 33_0402_5%

CLK

R294 1

C157
68P_0402_50V8K

74AHCT1G125GW_SOT353-5

+CRT_VCC

DAT

1
R105

R106
4.7K_0402_5%

4.7K_0402_5%

0_0402_5%

R104

R103
4.7K_0402_5%

4.7K_0402_5%
2
1

R102
2

+3VS

CRT_DDC_DATA <5>

Q3A
2N7002DW-T/R7_SOT363-6

R86

0_0402_5%

CLK

CRT_DDC_CLK <5>

Q3B
2N7002DW-T/R7_SOT363-6
4

R101 0_0402_5%
@

2010/05/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Title

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

CRT Connector
Size
B
Date:

Document Number

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC


Friday, December 03, 2010

Sheet
E

11

of

36

LCD POWER CIRCUIT


+3VS

+3VALW
+LCDVDD

W=60mils

1
100K_0402_5%

Q12
AO3413_SOT23-3

2 0_0402_5%

+LCDVDD

2N7002W-T/R7_SOT323-3
Q13

2
G

R110 1

1
ENVDD

ENVDD

<5>

4.7U_0805_10V4Z

0.1U_0402_16V4Z
1
1
@ C161
C343

R111
100K_0402_5%

4.7U_0805_10V4Z
2

@R114
@
R114 1

2 0_0402_5%

R115 1

2 0_0402_5%

<5> INV_PWM

2
R116

<5> ENBKL

C162

INVTPWM
EC_ENBKL <23>

0_0402_5%

0.1U_0402_16V4Z

R117
10K_0402_5%

<23> EC_INVT_PWM

1 2

2
R109

0.1U_0402_16V4Z
G

2
G

C160

C159

D
Q11
2N7002W-T/R7_SOT323-3

R108
100K_0402_5%

R107
300_0603_5%

+LCD_INV
C

B+

1.5A

L18

W=30mils

R113
2

+5VS

0_0603_5%
1

C169
68P_0402_50V8J

+5VS_LVDS_CAM

2
1
FBMA-L11-201209-221LMA30T_0805
1
C168
@C171
@
C171
680P_0402_50V7K
0.1U_0603_25V7K
2
2

Rated Current MAX:3000mA

C170
47P_0402_50V8J

<15> USB20_N1
<15> USB20_P1

<5>
<5>

LVDS_CLKLVDS_CLK+

<5>
<5>

LVDS_TX2LVDS_TX2+

<5>
<5>
<5>
<5>

LVDS_TX0LVDS_TX0+
LVDS_TX1LVDS_TX1+

INVTPWM

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

31

GND

GND

R120 1
R121 1

USB20_N1_R
USB20_P1_R

2 0_0402_5%
2 0_0402_5%

+LCD_INV
L20 @
+LCDVDD

+3VS

+5VS_LVDS_CAM
USB20_P1_R
USB20_N1_R

C431
C714
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2

WCM2012F2SF-121T04_0805

100K_0402_5%
R1191

BKOFF#

BKOFF# <23>

32

D28 @

<5> LVDS_DAT
<5> LVDS_SCL

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

CONN@
2 2
4 4
6 6
8 8
10 10
12 12
14 14
16 16
18 18
20 20
22 22
24 24
26 26
28 28
30 30

JLVDS

ACES_87242-3001-09

R112
10K_0402_5%

USB20_N1_R

USB20_P1_R

PJDLC05_SOT23-3

2010/05/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Title

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

LVDS & DVI Connector


Size Document Number
Custom

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC

Date:

Friday, December 03, 2010

Sheet
1

12

of

36

0.01U_0402_16V7K
SATA_ITX_C_DRX_P0 2
SATA_ITX_C_DRX_N0 2
0.01U_0402_16V7K

<18> SATA_ITX_C_DRX_P0
<18> SATA_ITX_C_DRX_N0

SATA for HDD1

AJ8
AH8

SATA_RX0N
SATA_RX0P

AH10
AJ10

SATA_TX1P
SATA_TX1N

AG10
AF10

SATA_RX1N
SATA_RX1P

AG12
AF12

SATA_TX2P
SATA_TX2N

AJ12
AH12

SATA_RX2N
SATA_RX2P

AH14
AJ14

SATA_TX3P
SATA_TX3N

AG14
AF14

SATA_RX3N
SATA_RX3P

AG17
AF17

SATA_TX4P
SATA_TX4N

AJ17
AH17

SATA_RX4N
SATA_RX4P

AJ18
AH18

SATA_TX5P
SATA_TX5N

AH19
AJ19

SATA_RX5N
SATA_RX5P

1 R122
1 R123

2 1K_0402_1%
2 931_0402_1%

SATA_CALRP
SATA_CALRN

10K_0402_5% 2
1 R124
SATA_LED#
<24> SATA_LED#

HW MONITOR

SATA_TX0P
SATA_TX0N

SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0

GPIOD

AH9
AJ9

SERIAL ATA

SATA_ITX_DRX_P0
SATA_ITX_DRX_N0

+3VS

AB14
AA14

SATA_CALRP
SATA_CALRN

AD11

SATA_ACT_L/GPIO67

AD16

SATA_X1

AC16

SATA_X2

27P_0402_50V8J

@
C5

Y3 @
2

@
C210
27P_0402_50V8J

<17>
<17>
<17>
<17>

FCH_SPI_DO
FCH_SPI_DI
FCH_SPI_CLK
FCH_SPI_CS1#
PAD T15

J5
E2
K4
K9
G2

SPI_DI/GPIO164
SPI_DO/GPIO163
SPI_CLK/GPIO162
SPI_CS1_L/GPIO165
ROM_RST_L/GPIO161

FC_OE_L/GPIOD145
FC_AVD_L/GPIOD146
FC_WE_L/GPIOD148
FC_CE1_L/GPIOD149
FC_CE2_L/GPIOD150
FC_INT1/GPIOD144
FC_INT2/GPIOD147

AF28
AG29
AG26
AF27
AE29
AF29
AH27

FC_ADQ0/GPIOD128
FC_ADQ1/GPIOD129
FC_ADQ2/GPIOD130
FC_ADQ3/GPIOD131
FC_ADQ4/GPIOD132
FC_ADQ5/GPIOD133
FC_ADQ6/GPIOD134
FC_ADQ7/GPIOD135
FC_ADQ8/GPIOD136
FC_ADQ9/GPIOD137
FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139
FC_ADQ12/GPIOD140
FC_ADQ13/GPIOD141
FC_ADQ14/GPIOD142
FC_ADQ15/GPIOD143

AJ27
AJ26
AH25
AH24
AG23
AH23
AJ22
AG21
AF21
AH22
AJ23
AF23
AJ24
AJ25
AG25
AH26

FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58

W7
V9
W8

TEMPIN0/GPIO171
TEMPIN1/GPIO172
TEMPIN2/GPIO173
TEMPIN3/TALERT_L/GPIO174
TEMP_COMM

B6
A6
A5
B5
C7

R129 1
R130 1
R131 1

2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%

VIN0/GPIO175
VIN1/GPIO176
VIN2/GPIO177
VIN3/GPIO178
VIN4/GPIO179
VIN5/GPIO180
VIN6/GBE_STAT3/GPIO181
VIN7/GBE_LED3/GPIO182

A3
B4
A4
C5
A7
B7
B8
A8

R281
R136
R133
R182

2
2
2
2

SPI ROM

1
1

AH28
AG28
AF26

W5
W6
Y9

@ R126
1M_0402_5%
SATA_X2

FC_CLK
FC_FBCLKOUT
FC_FBCLKIN

FANOUT0/GPIO52
FANOUT1/GPIO53
FANOUT2/GPIO54

SATA_X1

25MHZ_20PF_7A25000012

U6B

1 C173
1 C174

<18> SATA_DTX_C_IRX_N0
<18> SATA_DTX_C_IRX_P0

+1.1VS

NC1
NC2

APU_ALERT# <5>

1
1
1
1

R132 1
R127 1
R128 1

@
R125 1

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
DDR_VID
2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%

2 10K_0402_5%

G27
Y2

21807-A11-HUDSON-M1_FCBGA605
B

DDR_VID
DDR_VID

1.5V@
R134 1

DDR voltage

DDR_VID <31>
0

+1.5V

+1.35V

2 10K_0402_5%

2010/05/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Title

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

SATA,SPI,GPIO
Size Document Number
Custom

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC

Date:

Friday, December 03, 2010

Sheet
1

13

of

36

C176 150P_0402_50V8J

AA22
Y21
AA25
AA24
W23
V24
W24
W25

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N

2 0_0402_5%
2 0_0402_5%

CLK_PCIE_WAN_R
CLK_PCIE_WAN#_R

GPP_CLK3P
GPP_CLK3N

L24
L23

GPP_CLK4P
GPP_CLK4N

P25
M25

GPP_CLK5P
GPP_CLK5N

P29
P28

GPP_CLK6P
GPP_CLK6N

N26
N27

GPP_CLK7P
GPP_CLK7N

<18> CLK_SD_48M

33_0402_5%

CLK_SD_48M_R

CPU

T29
T28
2

LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME_L
LDRQ0_L
LDRQ1_L/CLK_REQ6_L/GPIO49
SERIRQ/GPIO48

LPC

T25
V25

INTE_L/GPIO32
INTF_L/GPIO33
INTG_L/GPIO34
INTH_L/GPIO35

GPP_CLK8P
GPP_CLK8N

L25

ALLOW_LDTSTP/DMA_ACTIVE_L
PROCHOT_L
LDT_PG
LDT_STP_L
LDT_RST_L

XTAL25_OUT

L27

25M_X1

Y1
25MHZ_20PF_7A25000012

G21
H21
K19
G22
J24

25M_X2

R153
10K_0402_5%

T34 PAD

CLK_PCI_EC_R
CLK_PCI_DB_R
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#

33_0402_5% 2
33_0402_5% 2

SERIRQ

APU_LDT_STP# <5>
APU_PROCHOT_FCH#
APU_PWRGD <5>

APU_PWRGD

<5>

C2

FCH_RTCX2

RTCCLK
INTRUDER_ALERT_L
VDDBT_RTC_G

D2
B2
B1

SUSCLK

<23>

R175 1

CLK_PCI_DB_R

2 510_0402_5%

C189
1U_0402_6.3V4Z

J10 @
JUMP_43X39

PCICLK1

C191
18P_0402_50V8J
2
1

PCICLK3

OSC

NC

OSC

C193
2
1

R177
20M_0603_5%

BAS40-04_SOT23

SP093MX0000

J3

Reserved

Reserved

LPC ROM

1 : Integrated clock mode. *


0 : Force PCIe interface at Gen I mode.*
1 : PCIe interface is at Gen II mode.
0 : Disable the boot fail timer function. *
1 : Enable the boot fail timer function.

1 : Select external Debug Straps.

1 : Reserved.

1 : Reserved (Hudson-1 does not support


the lower power mode).

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

+3VL

2010/05/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

2
1

SPI ROM

C354
0.1U_0402_16V7K

PAD-OPEN 2x2m

2
2

0
1

0 : Required setting for integrated clock mode.


HDA_SDOUT_R
+RTCVCC

1
1

18P_0402_50V8J

+CHGRTC

1
3

+CHGRTC

ROM TYPE

0 : Required setting for integrated clock mode.


PCICLK4

FCH_RTCX2

MAXEL_ML1220T10

NC

D29

R227
560_0603_5%
1
2

Description
0 : Integrated Microcontroller (IMC) Disabled

0 : Disable Debug Straps.


FCH_RTCX1

32.768KHZ_12.5PF_9H03200413
R178
560_0603_5%
1
2

R161
10K_0402_5%

PLT_RST_BUF# <19,20,23>

RTC Battery

R160
10K_0402_5%

0 : External clock mode.

R165
100K_0402_5%

+RTCBATT

R159
10K_0402_5%

R1554
120_0402_5%

X1

EC_PWM2

+RTCVCC

LDT_RST# <5>

32K_X2

R158
10K_0402_5%

EC_PWM3 EC_PWM2

<23>

R157
10K_0402_5%

1 : Integrated Microcontroller (IMC) Enabled

EC_PWM3

SERIRQ

NC7SZ08P5X_NL_SC70-5
@

PBJ1 @

CLK_PCI_EC <23>
CLK_PCI_DB <20>

PCICLK2
Y

CLK_PCI_EC_R

1 R172
1 R173

LPC_AD0 <20,23>
LPC_AD1 <20,23>
LPC_AD2 <20,23>
LPC_AD3 <20,23>
LPC_FRAME# <20,23>

0.1U_0402_16V7K

R156
10K_0402_5%
@

Net Name

U9
2 B

PLT_RST#

R155

T35 PAD
2

R248 @ 1
10K_0402_5%

FCH_RTCX1

2 0_0402_5%

+3VS
@
C187
1

PCICLK4
<15> HDA_SDOUT_R

C1

1 R162

C192 27P_0402_50V8J

PCICLK3

21807-A11-HUDSON-M1_FCBGA605

+3VS

@ R148
10K_0402_5%

PCICLK2

C188
0.1U_0402_16V7K

+3VS

R151
10K_0402_5%
@

CLK_PCI_DB_R

AJ6
AG6
AG4
AJ4

H24
H25
J27
J26
H29
H28
G28
J25
AA18
AB19

R154
@

+3VS

R147
10K_0402_5%
@

PCICLK1

32K_X1

XTAL25_OUT

EC_PWM2

+3VS

R146
10K_0402_5%
@

R176
1M_0402_5%

L26

RTC

XTAL25_IN

XTAL25_IN
27P_0402_50V8J

<15>

14M_25M_48M_OSC

C190

EC_PWM3

+3VS

@ R145
@R145
10K_0402_5%

GPP_CLK2P
GPP_CLK2N

R170 1
R171 1

<15>

+3VALW

R144
10K_0402_5%

GPP_CLK1P
GPP_CLK1N

<20> CLK_PCIE_WLAN
<20> CLK_PCIE_WLAN#

<17>
<17>
<17>
<17>
<17>

+3VS

@ R143
@R143

N29
N28
M29
M28

CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R

CLK_PCI_EC_R
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27

+3VS

R142
@

GPP_CLK0P
GPP_CLK0N

2 0_0402_5%
2 0_0402_5%

R174

L29
L28

R168 1
R169 1

<34>
D

SLT_GFX_CLKP
SLT_GFX_CLKN

APU_PWRGD_CORE

CPU_HT_CLKP
CPU_HT_CLKN

V23
T23

V21
T21

+3VALW

R141
10K_0402_5%
@

CLK_APU_R
CLK_APU#_R

Q14
2N7002W-T/R7_SOT323-3

NB_HT_CLKP
NB_HT_CLKN

2 0_0402_5% APU_PWRGD_Q

2.2K_0402_5%

NB_DISP_CLKP
NB_DISP_CLKN

T26
T27

CLOCK GENERATOR

U29
U28

APU_PWRGD 1 R137

PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN

AA1
AA4
AA3
AB1
AA5
AB2
AB6
AB5
AA6
AC2
AC3
AC4
AC1
AD1
AD2
AC6
AE2
AE1
AF8
AE3
AF1
AG1
AF2
AE9
AD9
AC11
AF6
AF4
AF3
AH2
AG2
AH3
AA8
AD5
AD8
AA10
AE8
AB9
AJ3
AE7
AC5
AF5
AE6
AE4
AE11
AH5
AH4
AC12
AD12
AJ5
AH6
AB12
AB11
AD7

2.2K_0402_5%

M23
P23

T17 PAD
T18 PAD

<19> CLK_PCIE_LAN
<19> CLK_PCIE_LAN#

AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
CBE0_L
CBE1_L
CBE2_L
CBE3_L
FRAME_L
DEVSEL_L
IRDY_L
TRDY_L
PAR
STOP_L
PERR_L
SERR_L
REQ0_L
REQ1_L/GPIO40
REQ2_L/CLK_REQ8_L/GPIO41
REQ3_L/CLK_REQ5_L/GPIO42
GNT0_L
GNT1_L/GPO44
GNT2_L/GPO45
GNT3_L/CLK_REQ7_L/GPIO46
CLKRUN_L
LOCK_L

2.2K_0402_5%

1 0_0402_5%
1 0_0402_5%

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N

PCIE_CALRP
PCIE_CALRN

AA28
AA29
Y29
Y28
Y26
Y27
W28
W29

CLK_APU_DP_R
CLK_APU_DP#_R

1 0_0402_5%
1 0_0402_5%

R166 2
R167 2

<5> CLK_APU
<5> CLK_APU#

AD29
AD28

PCIE_CALRP
PCIE_CALRN

+3VS

R135
10K_0402_5%

PAD T16

2.2K_0402_5%

R163 2
R164 2

<5> CLK_APU_DP
<5> CLK_APU_DP#

UMI_RX0P
UMI_RX0N
UMI_RX1P
UMI_RX1N
UMI_RX2P
UMI_RX2N
UMI_RX3P
UMI_RX3N

PCI I/F

2 590_0402_1%
2 2K_0402_1%

AE24
AE23
AD25
AD24
AC24
AC25
AB25
AB24

V2

R149 1
R152 1

+1.1VS

UMI_C_TXP0
UMI_C_TXN0
UMI_C_TXP1
UMI_C_TXN1
UMI_C_TXP2
UMI_C_TXN2
UMI_C_TXP3
UMI_C_TXN3

PCIRST_L

+1.8VS
PCICLK1
PCICLK2
PCICLK3
PCICLK4

<6> UMI_C_TXP[0..3]
<6> UMI_C_TXN[0..3]

UMI_TX0P
UMI_TX0N
UMI_TX1P
UMI_TX1N
UMI_TX2P
UMI_TX2N
UMI_TX3P
UMI_TX3N

W2
W1
W3
W4
Y1

AD26
AD27
AC28
AC29
AB29
AB28
AB26
AB27

PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCICLK4/14M_OSC/GPO39

2
2
2
2
2
2
2
2

U6E
P1 False
PCIE_RST_L
L1 A_RST_L

UMI_RXP0
UMI_RXN0
UMI_RXP1
UMI_RXN1
UMI_RXP2
UMI_RXN2
UMI_RXP3
UMI_RXN3

PCI EXPRESS I/F

1
1
1
1
1
1
1
1

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

<6> UMI_C_RXP[0..3]
<6> UMI_C_RXN[0..3]

C177
C178
C179
C180
C181
C182
C183
C184

1 0_0402_5%
1 33_0402_5%

PCI CLKS

UMI_C_RXP0
UMI_C_RXN0
UMI_C_RXP1
UMI_C_RXN1
UMI_C_RXP2
UMI_C_RXN2
UMI_C_RXP3
UMI_C_RXN3

R140 2
R150 2

PLT_RST#

2 0_0402_5%

R138 1

Title

UMI,PCIE,CLK,PCI,LPC,RTC,CPU
Size Document Number
Custom

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC

Date:

Friday, December 03, 2010


1

Sheet

14

of

36

+3VALW
U6A

PAD T24
<19,20> FCH_PCIE_WAKE#
<5> APU_THERMTRIP#

NB_PWRGD
FCH_RSMRST#

<20> WLAN_CLKREQ1#
PAD T25

USB_OC#0

USB_FSD0P/GPIO185
USB_FSD0N

H9
J8

USB_HSD13P
USB_HSD13N

B12
A12

USB_HSD12P
USB_HSD12N

F11
E11

USB_HSD11P
USB_HSD11N

E14
E12

USB_HSD10P
USB_HSD10N

J12
J14

USB_HSD9P
USB_HSD9N

A13
B13

USB20_P9 <25>
USB20_N9 <25>

USB_HSD8P
USB_HSD8N

D13
C13

USB20_P8 <25>
USB20_N8 <25>

USB(USB/B2)

USB_HSD7P
USB_HSD7N

G12
G14

USB20_P7 <20>
USB20_N7 <20>

BT(MINI CARD)

USB_HSD6P
USB_HSD6N

G16
G18

USB_HSD5P
USB_HSD5N

D16
C16

USB_HSD4P
USB_HSD4N

B14
A14

USB_HSD3P
USB_HSD3N

E18
E16

USB_HSD2P
USB_HSD2N

J16
J18

USB20_P2 <18>
USB20_N2 <18>

CardReader

USB_HSD1P
USB_HSD1N

B17
A17

USB20_P1 <12>
USB20_N1 <12>

Camera

USB_HSD0P
USB_HSD0N

A16
B16

USB20_P0 <25>
USB20_N0 <25>

USB(MB)

SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
EC_PWM0/EC_TIMER0/GPIO197
EC_PWM1/EC_TIMER1/GPIO198
EC_PWM2/EC_TIMER2/GPIO199
EC_PWM3/EC_TIMER3/GPIO200

D25
F23
B26
E26
F25
E22
F22
E21

KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208

G24
G25
E28
E29
D29
D28
C29
C28

GBE_PHY_INTR
PAD T32
PAD T33
PAD T26

GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
GBE_RXCLK
GBE_RXD3
GBE_RXD2
GBE_RXD1
GBE_RXD0
GBE_RXCTL/RXDV
GBE_RXERR
GBE_TXCLK
GBE_TXD3
GBE_TXD2
GBE_TXD1
GBE_TXD0
GBE_TXCTL/TXEN
GBE_PHY_PD
GBE_PHY_RST_L
GBE_PHY_INTR

KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217
KSO_9/GPIO218
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/GPIO223
KSO_15/GPIO224
KSO_16/GPIO225
KSO_17/GPIO226

B28
A27
B27
D26
A26
C26
A24
B25
A25
D24
B24
C24
B23
A23
D22
C22
A22
B22

E23
E24
F21
G29

PS2_DAT/SDA4/GPIO187
PS2_CLK/SCL4/GPIO188
SPI_CS2_L/GBE_STAT2/GPIO166
FC_RST_L/GPO160

D27
F28
F29
E27

PS2KB_DAT/GPIO189
PS2KB_CLK/GPIO190
PS2M_DAT/GPIO191
PS2M_CLK/GPIO192

EMBEDDED CTRL

GBE_RXERR

T1
T4
L6
L5
T9
U1
U3
T2
U2
T5
V5
P5
M5
P9
T7
P7
M7
P4
M9
V7

AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167
AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169
AZ_SDIN3/GPIO170
AZ_SYNC
AZ_RST_L

GBE LAN

1 10K_0402_5%

1 10K_0402_5%

R186

1 200K_0402_5%

USB_OC#7

R183 2

1 200K_0402_5%

SCL3_LV

R187 2

1 10K_0402_5%

SDA3_LV

R188 2

1 10K_0402_5%

SMB_FCH_CK1

R184 1

2 2.2K_0402_5%

SMB_FCH_DA1

R185 1

2 2.2K_0402_5%

FCH_PCIE_WAKE# R189 2

1 10K_0402_5%

USB(USB/B1)

SMB_FCH_CK0

R190 1

2 2.2K_0402_5%

SMB_FCH_DA0

R191 1

2 2.2K_0402_5%

NB_PWRGD

1
R192

2
4.7K_0402_5%

SCL2

2
R193
2
R194
1
R195
2
R196
2
R197
2
R198

1
10K_0402_5%
1
10K_0402_5%
2
2.2K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%

SDA2
EC_RSMRST#
GBE_COL
GBE_CRS
GBE_RXERR

SCL2
SDA2

R199 2

1 0_0402_5%

EC_RSMRST# <23>

SCL3_LV <5>
SDA3_LV <5>
EC_PWM2 <14>
EC_PWM3 <14>

R209 2

1 0_0402_5%

+3VS @
C194 0.1U_0402_16V7K
1
2

M3
N1
L2
M2
1 10K_0402_5%
M1
M4
2 33_0402_5% HDA_SYNC_R N2
2 33_0402_5% HDA_RST#_R P2

GBE_MDIO

R181

FCH_RSMRST#

2 33_0402_5%HDA_BITCLK_R
2 33_0402_5%HDA_SDOUT_R

GBE_COL
GBE_CRS

R179

GBE_MDIO

+3VS

<34> FCH_PWROK

R206 1
R207 1

<21> HDA_SYNC
<21> HDA_RST#

USB_FSD1P/GPIO186
USB_FSD1N

J10
H11

@R205
@
R205 2

GBE_PHY_INTR

2 11.8K_0402_1%

1 10K_0402_5%

HD AUDIO

R201 1
R202 1

<21> HDA_BITCLK
<21> HDA_SDOUT
<21> HDA_SDIN0
<14> HDA_SDOUT_R

BLINK/USB_OC7_L/GEVENT18_L
USB_OC6_L/IR_TX1/GEVENT6_L
USB_OC5_L/IR_TX0/GEVENT17_L
USB_OC4_L/IR_RX0/GEVENT16_L
USB_OC3_L/AC_PRES/TDO/GEVENT15_L
USB_OC2_L/TCK/GEVENT14_L
USB_OC1_L/TDI/GEVENT13_L
USB_OC0_L/TRST_L/GEVENT12_L

1 R180

Y
3

<25>

CLK_REQ4_L/SATA_IS0_L/GPIO64
CLK_REQ3_L/SATA_IS1_L/GPIO63
SMARTVOLT1/SATA_IS2_L/GPIO50
CLK_REQ0_L/SATA_IS3_L/GPIO60
SATA_IS4_L/FANOUT3/GPIO55
SATA_IS5_L/FANIN3/GPIO59
SPKR_GPIO66
SCL0_GPIO43
SDA0_GPIO47
SCL1_GPIO227
SDA1_GPIO228
CLK_REQ2_L/FANIN4_GPIO62
CLK_REQ1_L/FANOUT4_GPIO61
IR_LED_L/LLB_L/GPIO184
SMARTVOLT2/SHUTDOWN_L/GPIO51
DDR3_RST_L/GEVENT7_L
GBE_LED0/GPIO183
GBE_LED1/GEVENT9_L
GBE_LED2/GEVENT10_L
GBE_STAT0/GEVENT11_L
CLK_REQG_L/GPIO65_OSCIN

PAD T20
USB_PCOMP

USB_OC#0

USB OC

H3
D1
E4
D4
E8
F7
E7
F8

<25> USB_OC#7
<23> EC_LID_OUT#

G19

USB 2.0

<21>
FCH_SPK
<8,9> SMB_FCH_CK0
<8,9> SMB_FCH_DA0
<20> SMB_FCH_CK1
<20> SMB_FCH_DA1

A10

USB_RCOMP

RSMRST_L

GPIO

AD19
AA16
AB21
AC18
AF20
AE19
AF19
AD22
AE22
F5
F4
AH21
AB18
E1
AJ21
H4
D5
D7
G5
K3
AA20

<19> LAN_CLKREQ0#

@R200
@
R200 2

G1

USBCLK/14M_25M_48M_OSC

USB 1.1

<23>
<23>
<23>
<23>

T29 PAD
T30 PAD
T31 PAD
GATEA20
KB_RST#
EC_SCI#
EC_SMI#

USB MISC

FCH_PWROK

PCI_PME_L/GEVENT4_L
RI_L/GEVENT22_L
SPI_CS3_L/GBE_STAT1/GEVENT21_L
SLP_S3_L
SLP_S5_L
PWR_BTN_L
PWR_GOOD
SUS_STAT_L
TEST0
TEST1/TMS
TEST2
GA20IN/GEVENT0_L
KBRST_L/GEVENT1_L
LPC_PME_L/GEVENT3_L
LPC_SMI_L/GEVENT23_L
GEVENT5_L
SYS_RESET_L/GEVENT19_L
WAKE_L/GEVENT8_L
IR_RX1/GEVENT20_L
THRMTRIP_L/SMBALERT_L/GEVENT2_L
NB_PWRGD

ACPI/WAKE UP EVENTS

<23> FCH_SLP_S3#
<23> FCH_SLP_S5#
<23> PBTN_OUT#

J2
K1
D3
F1
H1
F2
H5
G6
B3
C4
F6
AD21
AE21
K2
J29
H2
J1
H6
F3
J6
AC19

EC_FCH_PWROK

<23>

VGATE <23,34>

NC7SZ08P5X_NL_SC70-5
U10 @

21807-A11-HUDSON-M1_FCBGA605

2009/02/04

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/02/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

USB,GPIO,GLAN,HDA
Size Document Number
Custom

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC

Date:

Friday, December 03, 2010

Sheet
1

15

of

36

+3VS
D

+3VS_SB

0_0603_5%

2
22U_0805_6.3V6M

2
2
0.1U_0402_16V4Z

+3VS

220
_0.2A
DCR:0.2

+3VS_PCIE_VDDPL

L22 1
2
FBMA-L11-160808-221LMT_2P
C209
2.2U_0402_6.3VM

0.1U_0402_16V4Z
1
C211

2
1U_0402_6.3V6K

220
_0.2A
DCR:0.2

+3VS_SATA_VDDPL

15.5mA

L24 1
2
FBMA-L11-160808-221LMT_2P
C217
2.2U_0402_6.3VM

AD14

VDDPL_33_SATA

0.1U_0402_16V4Z AJ20
AF18
AH20
2
2
AG19
120
_5A
+1.1VS
+1.1VS_SATA
AE18
1354.2mA
DCR:0.02

AD18
1U_0402_6.3V6K 0.1U_0402_16V4Z
L25 1
2
AE16
FBMA-L11-201209-121LMA50
1
1
1
1
1
C222
C223
C224
C225
C226
22U_0805_6.3V6M
0.1U_0402_16V4Z

+3VALW

220
_3A
DCR:0.04

+3VALW_USB_AVDD

C229
10U_0603_6.3V6M

2
2
1U_0402_6.3V6K

534.5mA

1U_0402_6.3V6K
0.1U_0402_16V4Z
1
1
1
1
C231
C232
C233

1
C230

+1.1VALW

2
1U_0402_6.3V6K

+1.1VALW_USB_VDDAN

L28 1
2
FBMA-L11-160808-221LMT_2P

220
_0.2A
DCR:0.2

C237
2.2U_0402_6.3VM

88.6mA
1

C238
0.1U_0402_16V4Z

2
2
0.1U_0402_16V4Z

2
1U_0402_6.3V6K

A18
A19
A20
B18
B19
B20
C18
C20
D18
D19
D20
E19

VDDAN_33_USB_S_1
VDDAN_33_USB_S_2
VDDAN_33_USB_S_3
VDDAN_33_USB_S_4
VDDAN_33_USB_S_5
VDDAN_33_USB_S_6
VDDAN_33_USB_S_7
VDDAN_33_USB_S_8
VDDAN_33_USB_S_9
VDDAN_33_USB_S_10
VDDAN_33_USB_S_11
VDDAN_33_USB_S_12

C11
D11

VDDAN_11_USB_S_1
VDDAN_11_USB_S_2

2
1U_0402_6.3V6K

1 0_0603_5%

2 R214

1 0_0603_5%

VDDCR_11_GBE_S_1
VDDCR_11_GBE_S_2

L7
L9

2 R215

1 0_0603_5%

VDDIO_GBE_S_1
VDDIO_GBE_S_2

M6
P8

2 R216

1 0_0603_5%

120
_5A
DCR:0.02

VDDPL_33_SYS

M21

VDDPL_11_SYS_S

L22

VDDPL_33_USB_S

F19

VDDXL_33_S

C220

C221

+3VALW

0_0603_5%

2
2.2U_0402_6.3VM

2
+1.1VALW

0.1U_0402_16V4Z

2 R218

C246

C227

C228

1U_0402_6.3V6K

16.1mA
11.4mA
5.0mA

2
1U_0402_6.3V6K

+1.1VALW_USB_VDDCR

C236
0.1U_0402_16V4Z

+3VS_VDDPL

1 0_0603_5%

+VDDIO_AZ

65.3mA

D6

46.5mA

VDDAN_33_HWM_S

+1.1VALW_VDDP

+1.1VALW

+3VALW_USB_AVDD

C235

C234

2
0.1U_0402_16V4Z

L27 1
2
FBMA-L11-160808-221LMT_2P

10U_0603_6.3V6M

220
_0.2A
DCR:0.2

+3VALW

L20

21807-A11-HUDSON-M1_FCBGA605

220
_0.2A
DCR:0.2

+3VS_VDDXL

C240
0.1U_0402_16V4Z

+3VS

L29 1
2
FBMA-L11-160808-221LMT_2P

+VDDIO_AZ

C239
2.2U_0402_6.3VM
C241
2.2U_0402_6.3VM

220
_0.2A +3VS
DCR:0.2

+3VS_VDDPL

C242
2.2U_0402_6.3VM

L32 1
2
FBMA-L11-160808-221LMT_2P
1
C243

2.2U_0402_6.3VM

58mA

A11
B11

1
C186
@

ESR:9ohm(MAX)

0.1U_0402_16V4Z 1
C219

15.3mA

VDDCR_11_USB_S_1
VDDCR_11_USB_S_2

2 R217

F26
G26
M8

+3VALW_VDDIO

A21
D21
B21
K10
L10
J9
T6
T8

165.2mA

VDDIO_AZ_S

+1.1VS

2
22U_0805_6.3V6M

49.5mA

VDDCR_11_S_1
VDDCR_11_S_2

+1.1VS

C185

2
2
0.1U_0402_16V4Z

2 R213

VDDIO_33_S_1
VDDIO_33_S_2
VDDIO_33_S_3
VDDIO_33_S_4
VDDIO_33_S_5
VDDIO_33_S_6
VDDIO_33_S_7
VDDIO_33_S_8

10U_0603_6.3V6M

+1.1VS_CLK

C208

+1.1VS
R211 2
0_0805_5%

L34 1
1U_0402_6.3V6K
2
1
1 FBMA-L11-201209-121LMA50
C205
C204

0.1U_0402_16V4Z
1
1
C207
C206

M10

PLL

2
2
10U_0603_6.3V6M

+1.1VALW_VDDCR

USB I/O

L26 1
2
FBMA-L11-201209-221LMA30T_0805

VDDAN_11_SATA_1
VDDAN_11_SATA_4
VDDAN_11_SATA_2
VDDAN_11_SATA_3
VDDAN_11_SATA_5
VDDAN_11_SATA_6
VDDAN_11_SATA_7

CORE S5

C218

VDDAN_11_PCIE_1
VDDAN_11_PCIE_2
VDDAN_11_PCIE_3
VDDAN_11_PCIE_4
VDDAN_11_PCIE_5
VDDAN_11_PCIE_6
VDDAN_11_PCIE_7
VDDAN_11_PCIE_8

3.3V_S5 I/O

U26
V22
V26
V27
V28
V29
W22
W26

GBE LAN

1115.6mA

1U_0402_6.3V6K
0.1U_0402_16V4Z
1
1
1
1
C213
C214
C215
C216
@

VDDPL_33_PCIE

C203

0.1U_0402_16V4Z
1U_0402_6.3V6K
1
1
1
1
C202
C201
C200
C199

V1

VDDRF_GBE_S

SERIAL ATA

+3VS

AE28

0.1U_0402_16V4Z

C212
22U_0805_6.3V6M

+1.1VS_PCIE

VDDAN_11_CLK_1
VDDAN_11_CLK_2
VDDAN_11_CLK_3
VDDAN_11_CLK_4
VDDAN_11_CLK_5
VDDAN_11_CLK_6
VDDAN_11_CLK_7
VDDAN_11_CLK_8

K28
K29
J28
K26
J21
J20
K21
J22

VDDIO_33_GBE_S

PCI EXPRESS

120
_5A
DCR:0.02

L23 1
2
FBMA-L11-201209-121LMA50

VDDIO_18_FC_1
VDDIO_18_FC_2
VDDIO_18_FC_3
VDDIO_18_FC_4

N13
R15
N17
U13
U17
V12
V18
W12
W18

382.9mA

22.5mA
2

+1.1VS

AF22
AE25
AF24
AC22

FLASH I/O

0.16mA

979.4mA

VDDCR_11_1
VDDCR_11_2
VDDCR_11_3
VDDCR_11_4
VDDCR_11_5
VDDCR_11_6
VDDCR_11_7
VDDCR_11_8
VDDCR_11_9

330U_D2_2.5VY_R9M

+1.1VS_VDDCR

POWER

VDDIO_33_PCIGP_1
VDDIO_33_PCIGP_2
VDDIO_33_PCIGP_3
VDDIO_33_PCIGP_4
VDDIO_33_PCIGP_5
VDDIO_33_PCIGP_6
VDDIO_33_PCIGP_7
VDDIO_33_PCIGP_8
VDDIO_33_PCIGP_9
VDDIO_33_PCIGP_10
VDDIO_33_PCIGP_11
VDDIO_33_PCIGP_12

330U_D2_2.5VY_R9M

2 0_0402_5%

AH1
V6
Y19
AE5
AC21
AA2
AB4
AC8
AA7
AA9
AF7
AA19

CLKGEN I/O

R212

U6C

42mA

PCI/GPIO I/O

0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
C195
C196
C197
C198

CORE S0

2 R210

0.1U_0402_16V4Z

+1.1VALW_VDDP

C244
2.2U_0402_6.3VM

R219 2
R220 2
@

1 0_0603_5%
1 0_0603_5%

+3VALW
+1.5V

+3VALW

220
_0.2A +1.1VALW
DCR:0.2

L30 1
2
FBMA-L11-160808-221LMT_2P
1
C245

0.1U_0402_16V4Z

C247

close pin D6

0.1U_0402_16V4Z

2009/02/04

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/02/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

PWR
Size Document Number
Custom

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC

Date:

Friday, November 26, 2010

Sheet
1

16

of

36

U6D

FCH_SPI_CS1#
@
C928
10P_0402_50V8J

FCH_SPI_DO

For EMI close U59

U20 FROM@

<13>
<13>
<13>
<13>
+3VS
+3VALW

FCH_SPI_DO
FCH_SPI_CS1#
FCH_SPI_CLK
FCH_SPI_DI

R1557 FROM@ 2
R1558
@ 2

1
1

0_0402_5%
0_0402_5%

1
4
10
13

1OE#
2OE#
3OE#
4OE#

2
5
9
12

1A
2A
3A
4A

14

VCC

FCH_SPI_DO_R

FCH_SPI_DI_R

3
6
8
11

1B
2B
3B
4B

FCH_SPI_CLK_R
FCH_SPI_CS1#_R

+3V_SPI

GND

SN74CBT3125PWRG4_TSSOP14
C595
0.1U_0402_16V4Z
FROM@

1
U21
FCH_SPI_CS1#_R
FCH_SPI_DO_R

U22
<23,24,29> EC_ON

<23,24>
<23,24>
<23,24>
<23,24>

KSI3
KSI7
KSI6
KSI5
+3V_SPI

+3V_SPI

FROM@

1
4
10
13

1OE#
2OE#
3OE#
4OE#

2
5
9
12

1A
2A
3A
4A

14

VCC

1
2
3
4

CS#
VCC
DO(IO1) HOLD#(IO3)
WP#(IO2)
CLK
GND
DI(IO0)

FCH_SPI_CLK_R
FCH_SPI_DI_R

W25Q16BVSSIG_SO8

3
6
8
11

1B
2B
3B
4B

GND

SN74CBT3125PWRG4_TSSOP14

M20
+3VS

H23
H26
AA21
AA23
AB23
AD23
AA26
AC26
Y20
W21
W20
AE26
L21
K20

R1549 ROM@
1

+3V_SPI

+3VALW

0_0402_5%

R1556 @
1

+3V_SPI

0_0402_5%
+5VALW

+5VALW
C436 FROM@
2

1
R420

+5VALW

2
100K_0402_5%
FROM@

EC_ON

R416 FROM@
10K_0402_5%

0.1U_0402_16V4Z
U142A FROM@

R418 FROM@
100K_0402_5%

LM393DG_SO8

C435

0.1U_0402_16V4Z

+5VALW

LM393DG_SO8

2
1

Q28 FROM@
AO3416_SOT23-3

2
G

+3V_SPI

C434 FROM@
0.1U_0402_16V4Z

R417 FROM@
100K_0402_5%

2
1

1 : Use internal PLL-generated PLL CLK

U142B
FROM@
O 7

D6 FROM@
RB715F_SOT323-3
2
1
3

FROM@
R421
10K_0402_5%

+3VALW

FROM@

FROM@

0 : Bypass internal PLL clock

FROM@
R419
10K_0402_5%

+5VALW

1 10K_0402_5%
2

Description

R422 2

<23,26,30,33> SUSP#

+5VALW

2
B

PCI_AD27

8
7
6
5

C593
0.1U_0402_16V4Z

C594
0.1U_0402_16V4Z
FROM@

21807-A11-HUDSON-M1_FCBGA605

Net Name

2MB

VSSIO_PCIECLK_14
VSSIO_PCIECLK_15
VSSIO_PCIECLK_16
VSSIO_PCIECLK_17
VSSIO_PCIECLK_18
VSSIO_PCIECLK_19
VSSIO_PCIECLK_20
VSSIO_PCIECLK_21
VSSIO_PCIECLK_22
VSSIO_PCIECLK_23
VSSIO_PCIECLK_24
VSSIO_PCIECLK_25
VSSIO_PCIECLK_26
VSSIO_PCIECLK_27

1 0_0402_5%
ROM@
1 0_0402_5%
ROM@
2 R1552 1 0_0402_5%
ROM@
2 R1553 1 0_0402_5%
ROM@

VSSIO_PCIECLK_1
VSSIO_PCIECLK_2
VSSIO_PCIECLK_3
VSSIO_PCIECLK_4
VSSIO_PCIECLK_5
VSSIO_PCIECLK_6
VSSIO_PCIECLK_7
VSSIO_PCIECLK_8
VSSIO_PCIECLK_9
VSSIO_PCIECLK_10
VSSIO_PCIECLK_11
VSSIO_PCIECLK_12
VSSIO_PCIECLK_13

2 R1551

P21
P20
M22
M24
M26
P22
P24
P26
T20
T22
T24
V20
J23

VSSPL_SYS

2 R1550

FCH_SPI_CLK

VSSXL

FCH_SPI_DI

VSSAN_HWM

M19

FCH_SPI_CLK 1
@
2
R1455
0_0402_5%

EFUSE

AJ2
A28
A2
E5
D23
E25
E6
F24
N15
R13
R17
T10
P10
V11
U15
M18
V19
M11
L12
L18
J7
P3
V4
AD6
AD4
AB7
AC9
V8
W9
W10
AJ28
B29
U4
Y18
Y10
Y12
Y11
AA11
AA12
G4
J4
G8
G9
M12
AF25
H7
AH29
V10
P6
N4
L4
L8

Y4
D8

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52

VSSIO_USB_1
VSSIO_USB_2
VSSIO_USB_3
VSSIO_USB_4
VSSIO_USB_5
VSSIO_USB_6
VSSIO_USB_7
VSSIO_USB_8
VSSIO_USB_9
VSSIO_USB_10
VSSIO_USB_11
VSSIO_USB_12
VSSIO_USB_13
VSSIO_USB_14
VSSIO_USB_15
VSSIO_USB_16
VSSIO_USB_17
VSSIO_USB_18
VSSIO_USB_19
VSSIO_USB_20
VSSIO_USB_21
VSSIO_USB_22
VSSIO_USB_23
VSSIO_USB_24
VSSIO_USB_25
VSSIO_USB_26
VSSIO_USB_27
VSSIO_USB_28

GND

A9
B10
K11
B9
D10
D12
D14
D17
E9
F9
F12
F14
F16
C9
G11
F18
D9
H12
H14
H16
H18
J11
J19
K12
K14
K16
K18
H19

VSSIO_SATA_1
VSSIO_SATA_2
VSSIO_SATA_3
VSSIO_SATA_4
VSSIO_SATA_5
VSSIO_SATA_6
VSSIO_SATA_7
VSSIO_SATA_8
VSSIO_SATA_9
VSSIO_SATA_10
VSSIO_SATA_11
VSSIO_SATA_12
VSSIO_SATA_13
VSSIO_SATA_14
VSSIO_SATA_15
VSSIO_SATA_16
VSSIO_SATA_17
VSSIO_SATA_18
VSSIO_SATA_19

Y14
Y16
AB16
AC14
AE12
AE14
AF9
AF11
AF13
AF16
AG8
AH7
AH11
AH13
AH16
AJ7
AJ11
AJ13
AJ16

0 : ILA auto run enable


PCI_AD26

1 : ILA auto run disable

<14> PCI_AD23
<14> PCI_AD24

0 : Bypass internal FC Clk


PCI_AD25

1 : Use internal PLL FC Clk

<14> PCI_AD25

<14> PCI_AD26

NEED CHECK

<14> PCI_AD27

R334

2.2K_0402_5%

R335

2.2K_0402_5%

R336

2.2K_0402_5%

R337

2.2K_0402_5%

R338

2.2K_0402_5%

0 : Getting the value from I2C EPROM

PCI_AD24

1 : Disable I2C ROM

NEED CHECK

0 : Reserved

PCI_AD23

2009/02/04

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

1 : Required setting (use ROMTYPE straps to


determine the ROM type)

2010/02/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

GND
Size Document Number
Custom

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC

Date:

Friday, December 03, 2010

Sheet
1

17

of

36

JHDD CONN@

SATA HDD Conn.

<13> SATA_ITX_C_DRX_P0
<13> SATA_ITX_C_DRX_N0

SATA_DTX_C_IRX_N0 C248
SATA_DTX_C_IRX_P0 C249

<13> SATA_DTX_C_IRX_N0
<13> SATA_DTX_C_IRX_P0

1
1

1
2
3
4
5
6
7

SATA_ITX_C_DRX_P0
SATA_ITX_C_DRX_N0
SATA_DTX_IRX_N0
SATA_DTX_IRX_P0

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS
+5VS

+3VS
0.1U_0402_16V4Z

1
C250
1000P_0402_50V7K

10U_0805_10V4Z

1
C251

1
C252

1
C253

C255
0.1U_0402_16V4Z
2 @

1U_0603_10V4Z

+5VS

1
C254

10U_0805_10V4Z

GND
A+
AGND
BB+
GND

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12
SANTA_190501-1_22P

SD,MMC,MS muti-function pin define


2

2 0_0402_5%
2 0_0402_5%

R221

R222

SP2

10_0402_5%

10_0402_5%

SP3

SD_CLK/MSD2_R
SD_WP/MS_CLK_R
C256
10P_0402_50V8J

1 R223
1 R224

SD_CLK/MSD2
SD_WP/MS_CLK

MDIO
PIN Name
SP1

SD_CLK/MSD2

SD_WP/MS_CLK

C257
10P_0402_50V8J

SD Card
PIN Name
SP1

MMC Card
PIN Name

MS Card
PIN Name
SP1

SP4

SP5
SP6

SP7
SP8
SP9

+3VS_CR_VCC

2 0_0603_5%

0.1U_0402_16V4Z

C261
SD_WP/MS_CLK
MS_INS#
SDDAT1
SDDAT0
MSD3

AV_PLL 20mil (+1.8V internal regulator)

REFE

2
3

DM
DP

4
5
6

3V3_IN
CARD_3V3
V18

XD_CD#

8
9
10
11
12

SP1
SP2
SP3
SP4
SP5

25

C259
4.7U_0805_10V4Z

1U_0603_10V4Z

+VCC_OUT

1 C260

<15> USB20_N2
<15> USB20_P2

40mil
1 R226

+3VS

SP10

U11

EPAD

R225 1

1 C258 @ 100P_0402_50V8J
6.19K_0402_1%
2

GPIO0

17

CLK_IN

24

XD_D7

23

SP14
SP13
SP12
SP11
SP10
SP9
SP8
SP7
SP6

22
21
20
19
18
16
15
14
13

SP11
SP12

CLK_SD_48M <14>

SP13
SP14

MS_BS
SDDAT2
SDDAT3/MSD1

SP15

SD_CMD
MSD0
SD_CLK/MSD2

SP17

SD_CD#

JREAD
SD_WP/MS_CLK_R
SDDAT1
SDDAT0

RTS5138-GR_QFN24_4X4

MS_BS
SD_CLK/MSD2_R
SDDAT3/MSD1
MSD0
C262
2
1
22P_0402_50V8J

SD_CLK/MSD2_R
CLK_48M R361 2

CLK_SD_48M

0_0402_5%

MS_INS#
MSD3
SD_CMD
SD_WP/MS_CLK_R

+VCC_3IN1

40mil
+VCC_OUT

SDDAT3/MSD1

1 R229
2
0_0603_5%
1

0.1U_0402_16V4Z 2

SDDAT2
SD_CD#

1
C263

SP16

+VCC_3IN1

C265

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

SP18

CONN@

SD-WP
SD-DAT1
SD-DAT0
SD-GND
MS-GND
MS-BS
SD-CLK
MS-DAT1
MS-DAT0
SD-VCC
MS-DAT2
SD-GND
MS-INS
MS-DAT3
SD-CMD
MS-SCLK
MS-VCC
SD-DAT3
MS-GND
SD-DAT2 GND1
SD-CD
GND2

SP19

22
23

TAITW_R009-025-LR_NR

2 0.1U_0402_16V4Z

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/02/04

2010/02/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

HDD Connector
Size Document Number
Custom

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC

Friday, December 03, 2010

Date:
G

Sheet

18
H

of

36

J2

U12 8105E@
C266 1

2 0.1U_0402_16V7K

PCIE_PTX_IRX_P2

22

HSOP

<6> PCIE_PTX_C_IRX_N2

C267 1

2 0.1U_0402_16V7K

PCIE_PTX_IRX_N2

23

HSON

17
18

HSIP
HSIN

<6> PCIE_ITX_C_PRX_P2
<6> PCIE_ITX_C_PRX_N2

LED3/EEDO
LED1/EESK
LED0

31
37
40

EECS/SCL
EEDI/SDA

30
32

@
1 1

R230 1
R231 1

2 10K_0402_5%
2 10K_0402_5%

Q16 AP2301GN_SOT23-3
@
3
1

+3VALW

+3VALW

<14> CLK_PCIE_LAN
<14> CLK_PCIE_LAN#

R235 @
1

+3V_LAN

10K_0402_5%
2

+3V_LAN

REFCLK_P
REFCLK_N
CKXTAL1

44

CKXTAL2

28

LANWAKEB

26

ISOLATEB

14
2 10K_0402_5% 15
2
38
1K_0402_5%

+LAN_VDDREG
R237

19
20
43

ENSWREG
R252
10K_0402_5%
@

PERSTB RTL8105E/8111E

LAN_X2

ISOLATEB

+3VS

CLKREQB

25

LAN_X1

<15,20> FCH_PCIE_WAKE#

8111E@
R240 1
1
R236

16

2.49K_0402_1%
2

LAN_CLKREQ0#

ENSWREG

34
35

VDDREG
VDDREG

46

RSET

24
49

GND
GND

13
29
41

+LAN_VDD10

DVDD33
DVDD33

27
39

+3V_LAN

AVDD33
AVDD33
AVDD33
AVDD33

12
42
47
48

+3V_LAN

EVDD10

21

+LAN_EVDD10

AVDD10
AVDD10
AVDD10
AVDD10

3
6
9
45

+LAN_VDD10

REGOUT

36

LAN_X2

NC

Pin14

NC

Pin15

NC

Pin38

1K ohm Pull-high

T27
LAN_MDI3LAN_MDI3+

1
2
3

LAN_MDI2LAN_MDI2+

4
5
6

TCT1
TD1+
TD1TCT2
TD2+
TD2-

24
23
22

R282

MCT2
MX2+
MX2-

21
20
19

R283

1 8111E@ 2 0_0402_5%

RJ45_MIDI3RJ45_MIDI3+

1 8111E@ 2 0_0402_5%

RJ45_MIDI2RJ45_MIDI2+

LAN_MDI1LAN_MDI1+

TCT3
TD3+
TD3-

MCT3
MX3+
MX3-

18
17
16

RJ45_MIDI1RJ45_MIDI1+

LAN_MDI0LAN_MDI0+

10
11
12

TCT4
TD4+
TD4-

MCT4
MX4+
MX4-

15
14
13

RJ45_MIDI0RJ45_MIDI0+

C289

+3V_LAN

RJ45_MIDI3-

PR4-

RJ45_MIDI3+

PR4+

RJ45_MIDI1-

PR2-

RJ45_MIDI2-

PR3-

RJ45_MIDI2+

PR3+

RJ45_MIDI1+

PR2+

RJ45_MIDI0-

PR1-

RJ45_MIDI0+

PR1+

C287 1000P_0402_50V7K
RJ45_GND
2
1
1
2
R1000
75_0402_1%

C272

1 0.1U_0402_16V4Z

C273

1 0.1U_0402_16V4Z

C274

1 0.1U_0402_16V4Z

C275

1 0.1U_0402_16V4Z

C386
2
8111E@

1 0.1U_0402_16V4Z

22U_0805_6.3V6M

+LAN_VDD10
C277
0.1U_0402_16V4Z
C

+LAN_VDD10

NC
C278

1 0.1U_0402_16V4Z

C279

1 0.1U_0402_16V4Z

C282

1 0.1U_0402_16V4Z

C284

1 0.1U_0402_16V4Z

C283

1 0.1U_0402_16V4Z 8111E@

C290

1 0.1U_0402_16V4Z 8111E@

C385

1 0.1U_0402_16V4Z 8111E@

+LAN_VDD10

R244
2 1U_0402_6.3V4Z
0_0603_5%

Close to Pin 21

+3V_LAN

SHLD1

SHLD2

10

1
C1000

C286
0.1U_0402_16V4Z

4.7U_0603_6.3V6K

Close to Pin 34 and 35

+LAN_VDDREG

1
C291

C292
0.1U_0402_16V4Z

LANGND

2 1000P_1808_3KV7K
1
C1001 @
2

C285

R245
2
0_0603_5%

SANTA_130452-C

+LAN_EVDD10

0.1U_0402_16V4Z

C1002 @
4.7U_0603_6.3V6K

U12

LANGND

For P/N and footprint


Please place them to ISPD page

D32

D33 @
AZC199-02S.R7G C/C SOT23

AZC199-02S.R7G C/C SOT23

R341 @
2
0_0603_5%

R358 @
2
0_0603_5%

8111E 10/100M/1000M
8111E@

Compal Secret Data

Security Classification
10/100M/1000M transformer
8111E@

2009/02/04

Issued Date

2010/02/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

10K ohm PD

X'FORM_ NS892404

0.1U_0603_25V7K

T27

@
C271
4.7U_0805_10V4Z

4.7UH_1008HC-472EJFS-A_5%_1008
2
1
1
C276

C281
33P_0402_50V8J

RJ45_GND

JLAN CONN@

MCT1
MX1+
MX1-

7
8
9

L33
1

Close to pin3, pin13, pin 29


and pin45.

8105E@

1
@C270
@
C270

+3V_LAN

L6 must be within 200mil to


Pin36, C276, C277must be
within 200mil to L6;
+LAN_REGOUT: Width=60mil

1
C280
33P_0402_50V8J

C269

+3V_LAN

0.01U_0402_25V7K

Close to Pin27,39,47 and 48.

RTL8111E

Pin12

1U_0402_6.3V4Z

47K_0402_5%

1
2

@
1

@
2

25MHZ_20PF_7A25000012

R243 @
0_0402_5%

R242
15K_0402_5%

<23> EN_WOL#

RTL8105E

Y2
LAN_X1

ENSWREG

ISOLATEB

R234

+LAN_REGOUT

1
R239
0_0402_5%

R238
1K_0402_1%

2
0.1U_0402_16V7K

R233 @

+LAN_REGOUT

USE SA00003PO00 footprint


06-30

+3VS

DVDD10
DVDD10
DVDD10

@
C268

100K_0402_5%

RTL8105E-VC-GR_QFN48_6X6

+3V_LAN

1
2
4
5
7
8
10
11

SMBCLK(NC)
SMBDATA(NC)
GPO/SMBALERT

33

LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1LAN_MDI2+
LAN_MDI2LAN_MDI3+
LAN_MDI3-

MDIP0
MDIN0
MDIP1
MDIN1
MDIP2(NC)
MDIN2(NC)
MDIP3(NC)
MDIN3(NC)

2 0_0402_5%

R232 1

<15> LAN_CLKREQ0#
<14,20,23> PLT_RST_BUF#

JUMP_43X79
2 2

<6> PCIE_PTX_C_IRX_P2

Title

Compal Electronics, Inc.


RTL8105E-VC-GR&RTL8111E-VB-GR

Size Document Number


Custom

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC

Date:

Sheet
1

19

of

36

+3V_WLAN

WLAN&BT

+3V_WLAN

2 WLAN_CLKREQ1#
10K_0402_5%

1
R246
@

R247

0_0805_5%

+3VS

+1.5VS
JWLAN
D

2 0_0402_5% WLAN_WAKE#

R249 1

<15,19> FCH_PCIE_WAKE#
<23> BT_PWR
<15> WLAN_CLKREQ1#
<14> CLK_PCIE_WLAN#
<14> CLK_PCIE_WLAN
C736

R357

CLK_PCI_DB

R251

<14,19,23> PLT_RST_BUF#
<14> CLK_PCI_DB
<6> PCIE_PTX_C_IRX_N3
<6> PCIE_PTX_C_IRX_P3

33P_0402_50V8J 33_0402_5%
@
@

<6> PCIE_ITX_C_PRX_N3
<6> PCIE_ITX_C_PRX_P3

R253

EC_TX_P80_DATA

+3V_WLAN
100K_0402_5%

<23> EC_TX_P80_DATA
<23> EC_RX_P80_CLK

+3V_WLAN

0_0402_5%

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

GND1

CONN@

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GND2

54

LPC_FRAME# <14,23>
LPC_AD3 <14,23>
LPC_AD2 <14,23>
LPC_AD1 <14,23>
LPC_AD0 <14,23>
WL_OFF# <23>
PLT_RST_BUF# <14,19,23>

R339 1
R340 1

2 0_0402_5%
2 0_0402_5%

SMB_FCH_CK1 <15>
SMB_FCH_DA1 <15>

USB20_N7 <15>
USB20_P7 <15>

+3VS

C294
+3V_WLAN

0.1U_0402_16V4Z

ACES_88910-5204

+1.5VS

H27
H_3P0

1
2

H3
H_3P0

0.1U_0402_16V7K

H25
H_3P0

C300

C301
47P_0402_50V8J
@

H26
H_6P2

H4
H_3P0

H_6P2
H_3P0

H24
H_3P0

0.1U_0402_16V7K

1
C298
C299
47P_0402_50V8J
@

1
2

H23
H_3P0

4.7U_0603_6.3V6K

C297

C296

C295

0.1U_0402_16V7K

0.1U_0402_16V7K

H1
H_3P4

H_3P4

FD2

FD3

FD4

H7
H_4P5

H8
H_4P5

H9
H_4P5

FD1

H10
H_4P5

H_4P5

H11
H_3P1N

H_3P1N

H20
H_4P1X3P1N
A

H_4P1X3P1N

2009/02/04

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/02/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

WLAN&BT&SCREW
Size Document Number
Custom

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC

Date:

Sheet
1

20

of

36

+PVDD1

0.1U_0402_16V4Z

1
C303

2 10U_0805_10V4Z

+DVDD_IO

+PVDD2

R310
0.1U_0402_16V4Z
1
C306

+3VS

1
0_0603_5%

+1.5VS

R257@
2
0_0603_5%

2 10U_0805_10V4Z

C309

1
C310
0.1U_0402_16V4Z
2

+3VS_DVDD

10U_0805_10V4Z

23
24

IN2

0.1U_0402_16V4Z

U26 @

IN1

O
3

<23> EC_MUTE#

2 0_0402_5%

25

38
AVDD2

AVDD1

46

21
22

MIC1_L
MIC1_R

HP_OUT_L
HP_OUT_R

32
33

MIC2_L_C
MIC2_R_C

16
17

MIC2_L
MIC2_R

4
11

2 100P_0402_50V8J

MONO_IN
SENSE_A

C323 1

39

MIC1_L_C
MIC1_R_C

PD#

PVDD2

45
44

<15> HDA_RST#
@
C322

DVDD_IO

SPK_OUT_R+
SPK_OUT_R-

2 2.2U_0603_6.3V4Z

MIC1_VREFO_L

12
13

2
10U_0805_10V4Z

PD#

Place close to chip

2
0.1U_0402_16V4Z

SENSE B

36

CBP

2 75_0402_1%
2 75_0402_1%

<22>
<22>

SPKR+
SPKR-

<22>
<22>

HP_L
HP_R

<25>
<25>

MIC1_R_C C317
MIC1_L_C C318

SDATA_IN

R265 1

2 33_0402_5%

HDA_SDIN0 <15>

R266 1

2 0_0402_5%

EAPD

2 0_0402_5%

1
C735

2 1K_0402_1%

MIC1_R <25>

R347 1

2 1K_0402_1%

MIC1_L <25>

4.7U_0805_10V4Z
MIC2_L_R R350 1
1
2

2 1K_0402_1%

MIC2_R_R R351 1

2 1K_0402_1%

MIC1_L_R

MIC2_L_C C430

<15>

MIC2_R_C C429

HDA_BITCLK <15>

EAPD

47
48

MONO_OUT

20

MIC2_VREFO

29

MIC2_VREFO

MIC1_VREFO_R
LDO_CAP

30
28

MIC1_VREFO_R

2 4.7K_0402_5% MIC1_VREFO_L

INT_MIC <22>

4.7U_0805_10V4Z

22P_0402_50V8J
HDA_SDOUT <15>

SPDIFO

2 4.7K_0402_5% MIC1_VREFO_R

R349 1

SDATA_OUT

HDA_SYNC
R353

4.7U_0805_10V4Z
1
2 MIC1_R_R R346

4.7U_0805_10V4Z

SENSE A

18

R261 1
R262 1

SPKL+
SPKL-

PCBEEP

43
42
49
7

10

RESET#

31

1
C316

C315

BCLK

GPIO1/DMIC_CLK

CBN

SYNC
GPIO0/DMIC_DATA

35

R259 REAL@
1
2 +5VS
0_0603_5%

R348 1

LINE2_L
LINE2_R

3
R355 1

14
15

SN74AHC1G08DCKR_SC70-5

C314

10U_0805_10V4Z

40
41

PD#

REAL@

SPK_OUT_L+
SPK_OUT_L-

HDA_RST#

C319

@R256
@
R256
2 0.1U_0402_16V4Z
+5VS
0_0603_5%
1
1
@ C308
C311
@

0.1U_0402_16V4Z

U13

LINE1_L
LINE1_R

+3VS
C558 @1

PVDD1

DVDD

2 10U_0805_10V4Z

C312

0_0603_5%

2
10U_0805_10V4Z

+AVDD

0.1U_0402_16V4Z
1
C313

2 10U_0805_10V4Z

R258

+3VS

1
@C307
@
C307

R255
2 0.1U_0402_16V4Z
+5VS
0_0603_5%
1
1
C304
C305

1
C302

J1
JUMP_43X39
@

R352 1

2 4.7K_0402_5% MIC2_VREFO

<23>

For P/N and footprint


Please place them to ISPD page
U13 VIA@

VREF

27

MIC1_VREFO_L

JDREF

19

R267 1 REAL@ 2 20K_0402_1%

PVSS2
PVSS1
DVSS2
DVSS1

CPVEE

34

C325 1

AVSS1
AVSS2

26
37

REAL@
1 C324

0.1U_0402_16V4Z

1
C326

R267 VIA@

2 2.2U_0603_6.3V4Z
2

S IC VT1802P QFN 48P CODEC

10U_0805_10V4Z

C327
2.2U_0603_6.3V4Z
3

5.1K_0402_1%

ALC259-GR_QFN48_7X7

<25> HP_PLUG#

R269 1

2 39.2K_0402_1%

<25> MIC_PLUG#

R268 1

2 20K_0402_1%

Sense Pin

Impredance

SENSE_A

USE SA00003QR00 footprint

R280

1 0_0603_5%

Headphone out

R286

1 0_0603_5%

EXT.MIC

R270

1 0_0603_5%

Function

Codec Signals

<23> EC_BEEP#

R260 1

2 47K_0402_5%

<15> FCH_SPK

R263 1

2 47K_0402_5%

C320

SENSE A

PORT-I (PIN 32,33)


PORT-I (PIN 21,22)

20K

@C331
@
C331

10K

MONO_IN

0.1U_0402_16V4Z

39.2K

R264
10K_0402_5%

0.1U_0603_50V7K

C321
0.1U_0402_16V4Z

5.1K
39.2K

SENSE B

20K
10K

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

5.1K

2009/02/04

2010/02/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

ALC259-GR
Size Document Number
Custom

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC

Friday, December 03, 2010

Date:
G

Sheet

21
H

of

36

R342
<21> SPKL+

SPKL+

10U_0805_10V4Z
1

2 0_0603_5%

PACDN042Y3R_SOT23-3

SPK_L1

2
1

C332

1 @
C333
1U_0402_6.3V4Z
2

@1

D16

ACES_87213-0400G

C334
R343
<21> SPKL-

SPKL-

SPKR+

2 0_0603_5%

2 10U_0805_10V4Z

SPK_L2

2 0_0603_5%

10U_0805_10V4Z
1

SPK_R1

SPK_L1
SPK_L2
SPK_R1
SPK_R2

R344
<21> SPKR+

1
2
3
4

1
2
3 GND 5
4 GND 6
JSPK CONN@

PACDN042Y3R_SOT23-3

2
1

C335

1 @
C336
1U_0402_6.3V4Z
2

@1

D17

C337
R345
<21> SPKR-

SPKR-

2 0_0603_5%

2 10U_0805_10V4Z

SPK_R2
2

<21> INT_MIC

D18
PACDN042Y3R_SOT23-3
@
MIC1 45@

1
2

1
2
WM-64PCY_2

use CYWM64P0110 footprint

2010/05/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Title

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

MIC & Speaker


Size
B
Date:

Document Number

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC


Friday, December 03, 2010

Sheet
E

22

of

36

Board ID / SKU ID Table for AD channel


+EC_AVCC
FBM-11-160808-601-T_0603
1
2
L40

C342

KB_RST#

KB_RST#

C350
2
1

1
R275
22P_0402_50V8J

GATEA20

<15> GATEA20

2
1
D20
@
RB751V-40_SOD323-2

<14>
<14,20>
<14,20>
<14,20>
<14,20>
<14,20>

2
0_0402_5%

SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

CLK_PCI_EC

<14> CLK_PCI_EC
+3VALW

<14,19,20> PLT_RST_BUF#

R276 1
2
47K_0402_5%
C351
0.1U_0402_16V4Z

EC_RST#
EC_SCI#

<15> EC_SCI#

2
<24>

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

KSO[0..15]

KSO[0..15]

KSI[0..7]

<17,24> KSI[0..7]

+3VALW

1
+3VALW

1
R287
1
R288

2
2

R284
R285

KSO1
2
47K_0402_5%
KSO2
2
47K_0402_5%

EC_SMB_CK1
2.2K_0402_5%
EC_SMB_DA1
2.2K_0402_5%

+3VS

1
R289
1
R290

EC_SMB_CK2
2.2K_0402_5%
EC_SMB_DA2
2
2.2K_0402_5%
1
C356
@
100P_0402_50V8J
2

C357
@
100P_0402_50V8J

<27>
<27>
<5>
<5>

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

1
2
3
4
5
7
8
10
12
13
37
20
38

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

EC_BEEP#

ACOFF
C352 1
2
0.01U_0402_16V7K

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

68
70
71
72

EN_FAN1
IREF
CHGVADJ

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
Interface
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F

83
84
85
86
87
88

EC_MUTE#
USB2_ON
BT_PWR
APU_PROCHOT_EC
TP_CLK
TP_DATA

SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

97
98
99
109

EN_WOL#
+1.1VS_ON
LID_SW#

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

119
120
126
128

FRD#SPI_SO
FWR#SPI_SI
SPI_CLK
FSEL#SPICS#

DA Output

77
78
79
80

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

PS2

ADP_I

0.250V

0.289V

0.436V

0.503V

0.538V

3
4

33K_5%

0.712V

0.819V

56K_5%

1.036V

1.185V

0.875V
1.264V

100K_5%

1.453V

1.650V

1.759V

200K_5%

2.200V

2.341V

NC

1.935V
2.500V

3.300V

3.300V

SPI Flash ROM

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
GPIO BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

73
74
89
90
91
92
93
95
121
127

<28>
BATT_TEMP <27>
<28>

+3VALW

MB_ID

MB_ID
C353
@

EC_MUTE# <21>
USB2_ON <25>
BT_PWR <20>
APU_PROCHOT_EC# <5>
TP_CLK <24>
TP_DATA <24>

R326

XCLK1
XCLK0

SPI_CLK_R

<24>

SPI_SI

SPI_CS#

1
R297
SPI_CLK_R
1
R298
SPI_SI
1
R300

FSEL#SPICS#
2
0_0402_5%
SPI_CLK
2
0_0402_5%
FWR#SPI_SI
2
0_0402_5%

KB926QFD3 LQFP 128P

ECAGND

SPI_CS#

<24>

R279
33K_0402_5%

Rb

FSTCHG <28>
BATT_FULL_LED# <24>
CAPS_LED# <25>
CHARGE_LOW_LED# <24>
PWR_ON_LED# <24>
SYSON <31>
VR_ON_EC <34>

R299
XCLKO 1
2 XCLKI
20M_0603_5%
@

LID_SW#

R118 1

2 100K_0402_5%

TP_CLK

R291 1

2 4.7K_0402_5%

TP_DATA R292 1

2 4.7K_0402_5%

BATT_TEMP

C359
@ 1
2 100P_0402_50V8J

FSTCHG

C360
@ 1
2 100P_0402_50V8J

EC_ENBKL

C362
@ 1
2 100P_0402_50V8J

SUSP#

C358
@ 1
2 100P_0402_50V8J

R293
100K_0402_5%

<15>

EC_ENBKL <12>
EAPD
<21>

SUSP#
PBTN_OUT#

ACIN_D

WL_OFF# <20>

C365
1
2 100P_0402_50V8J

R296
100K_0402_5%
@

SUSP# <17,26,30,33>
PBTN_OUT# <15>

R1555
+3VALW

1
ACIN_D

150K_0402_5%
2
D23

@
C364

ACIN

<28>

RB751V-40_SOD323-2

1 0.1U_0402_16V4Z

Signal

L41

EC_REV

KB926 D3 KB926 E0

EC_REV_SEL

OSC
NC

OSC
NC

Compal Secret Data

Security Classification

2009/02/04

Issued Date

Deciphered Date

2010/02/04

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C367 @
27P_0402_50V8J

X2@

Title

Compal Electronics, Inc.


ENE-KB926

Size Document Number


Custom

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC

Date:

Friday, December 03, 2010

Sheet

32.768KHZ_12.5PF_9H03200413
5

1
4

1
@ C366
27P_0402_50V8J

EC_FCH_PWROK
BKOFF# <12>

EC_ENBKL

FBM-11-160808-601-T_0603

EC_RSMRST# <15>
EC_LID_OUT# <15>
EC_ON <17,24,29>

EC_REV_SEL
WL_OFF#

4.7U_0805_10V4Z 1

+5VS

EC_FCH_PWROK
BKOFF#

PreMP

+3VALW

FRD#SPI_SO <24>

EC_RSMRST#
EC_LID_OUT#
EC_ON

PVT

VGATE <15,34>
EN_WOL# <19>
+1.1VS_ON <26>
LID_SW# <24>

FSTCHG
BATT_FULL_LED#
CAPS_LED#
CHARGE_LOW_LED#
PWR_ON_LED#
SYSON
VR_ON_EC
ACIN_D

C363

DVT

V18R

124

GPI

EVT

<24>

R330
100K_0402_5%

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

110
112
114
115
116
117
118

AGND

SUSCLK

122
123

<14>

XCLKI
2 XCLKO
0_0402_5%

100
101
102
103
104
105
106
107
108

69

EC_TX_P80_DATA
EC_RX_P80_CLK
ON/OFF_BTN#

<20> EC_TX_P80_DATA
<20> EC_RX_P80_CLK
<24> ON/OFF_BTN#

GND
GND
GND
GND
GND

EC_INVT_PWM
FAN_SPEED1

<12> EC_INVT_PWM
<5> FAN_SPEED1

11
24
35
94
113

WL_BT_LED#

<24> WL_BT_LED#

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

MB_ID

R278
100K_0402_5%

Ra
EN_FAN1 <5>
IREF
<28>
CHGVADJ <28>

+3VALW
FCH_SLP_S3#
FCH_SLP_S5#
EC_SMI#

<15> FCH_SLP_S3#
<15> FCH_SLP_S5#
<15> EC_SMI#

ECAGND

ADP_I

SPI Device Interface

SM Bus

0.216V

18K_5%

VAD_BRD min VAD_BRD typ VAD_BRD max


0V
0V
0V

EC_BEEP# <21>

63
64
65
66
75
76

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

8.2K_5%

ECAGND

21
23
26
27

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

1
2

PWM Output

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

67
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

AD

Rb / Rd

<15>

2
0_0402_5%

Board ID

1
R277

VCC
VCC
VCC
VCC
VCC
VCC

U14

0.1U_0402_16V4Z

100K_5%

AVCC

9
22
33
96
111
125

C347
1000P_0402_50V7K

C346
1000P_0402_50V7K

C349
0.1U_0402_16V4Z

C345
0.1U_0402_16V4Z

C344
0.1U_0402_16V4Z

C348
0.1U_0402_16V4Z

3.3V

Vcc
Ra

0_0805_5%

+EC_DVCC

R354

0.1U_0402_16V4Z

+3VALW

23

of

36

KSI[0..7]

INT_KBD Conn.

KSI[0..7] <17,23>

KSO[0..15]

KSO[0..15] <23>
+5VALW

KSO0
KSO1
KSO2
KSI7
KSI6
KSI5
KSI4
KSO3
KSO4
KSI3
KSI2
KSI1
KSI0
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

C398

JKB CONN@
GND 26
GND 27

JTP

25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

KSI3
KSI2
KSO0
KSI5

C368
C370
C372
C374

1
1
1
1

2
2
2
2

100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J

KSO6
KSO3
KSO12
KSO13

C369
C371
C373
C375

1
1
1
1

2
2
2
2

1
2
3
4
5
6
7
8
9
10
GND
GND

100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J

KSI6
KSI0
KSI1
KSO9

C376
C378
C380
C384

1
1
1
1

2
2
2
2

100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J

KSI4
KSO5
KSO1
KSI7

C377
C379
C381
C382

1
1
1
1

2
2
2
2

100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J

KSO2
KSO4
KSO7
KSO8

C387
C389
C392
C394

1
1
1
1

2
2
2
2

100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J

KSO14
KSO11
KSO10
KSO15

C388
C390
C393
C395

1
1
1
1

2
2
2
2

100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J

CONN@
1
2
3
4
5
6
7
8
9
10
11
12

0.1U_0402_16V4Z
+5VS
TP_CLK <23>
TP_DATA <23>
PWR_ON_LED# <23>
CHARGE_LOW_LED# <23>
BATT_FULL_LED# <23>
SATA_LED# <13>
WL_BT_LED# <23>

TP_CLK

C391
1
2 100P_0402_50V8J

TP_DATA

C396
1
2 100P_0402_50V8J

ACES_85201-1005N

ACES_85201-25051

Power BTN Board Conn

EC ROM

SPI_CLK_R
1
0_0402_5%

@
R304

2 C400 @
22P_0402_50V8J

7
8

+3VALW

JPWR1CONN@
1 1
ON/OFFBTN#
2 2
3 3
4 4
5
5
6 6

+3VALW
PWR_ON_LED# <23>
LID_SW# <23>

GND
GND
ACES_85201-0605N

1M-Bit
2

U15

+3VALW
SPI_CLK_R
SPI_SI

SPI_CLK_R <23>
SPI_SI <23>

MX25L1005AMC-12G_SO8

TOP SIDE

D31

ON/OFFBTN#

R322 @

BOT SIDE

100K_0402_5%

0_0603_5%

R308

R311 @

ON/OFF_BTN#

ON/OFF_BTN# <23>

1
3

51_ON#

<27>

BAV70W_SOT323-3

0_0603_5%
Q19
2N7002W-T/R7_SOT323-3
EC_ON

2
G
2

<17,23,29> EC_ON

8
7
6
5

2
C708
@
1000P_0402_50V7K
1

D30 @
RLZ20A_LL34

VCC
HOLD#
SCLK
SI

CS#
SO
WP#
GND

1
2
3
4

SPI_CS#
2SPI_SO
R303
0_0402_5%

<23> SPI_CS#
<23> FRD#SPI_SO

C399
0.1U_0402_16V4Z

R309
10K_0402_5%

2009/02/04

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/02/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

EC ROM&KB&TP&BTN
Size Document Number
Custom

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC

Date:

Friday, December 03, 2010

Sheet
1

24

of

36

USB PORT0
+USB_CS0
@
C405

USB2_ON#

C175

1 100P_0402_50V8J
1

+5VALW

C427

+5VALW

R307
10K_0402_5%

Q18

C403 1

2
G

2N7002W-T/R7_SOT323-3

USB2_ON <23>

1
2
3
4

0.1U_0402_16V7K

40 mils

USB2_ON#

U16

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

8
7
6
5

AP2301SG-13 SO

JUSB2 CONN@

+USB_CS0
<15>
<15>

0.1U_0402_16V7K

@ R305
@R305
@R306
@
R306

USB20_N0
USB20_P0

1
2
3
4
5
6
7
8

USB20_N0_R
USB20_P0_R

2 0_0402_5%
2 0_0402_5%

1
1
L42

C1003
+

1
1

1000P_0402_50V7K

1
2
4

150U_D2_6.3VY_R15M

1
4

1
2
3
4
GND
GND
GND
GND

ACON_UAR4E-4K1920

WCM2012F2SF-121T04_0805
R76

0_0402_5%
2

USB_OC#0 <15>

C164 @
4.7U_0805_10V4Z

D27
USB20_P0_R

USB20_N0_R

USB2_ON#

1
PJDLC05_SOT23-3

USB Conn
2

+USB_VCCA
JUSB CONN@

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+5VS
<23> CAPS_LED#
<15>
<15>

USB20_N9
USB20_P9

USB20_N9
USB20_P9

<15>
<15>

USB20_N8
USB20_P8

USB20_N8
USB20_P8

<21>
<21>

HP_R
HP_L

<21>
MIC1_L
<21>
MIC1_R
<21> HP_PLUG#
<21> MIC_PLUG#

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
G
G
ACES_85201-2005N

+USB_VCCA
+5VALW

AP2301SG-13 SO
R77
0_0402_5%
@
USB2_ON#

8
7
6
5

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

U19

1
2
3
4

C163

C432 1

0.1U_0402_16V7K

80 mils

USB_OC#7 <15>
4.7U_0805_10V4Z

2009/02/04

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/02/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

USB&USB/B CONN&LED
Size Document Number
Custom

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC

Date:

Friday, December 03, 2010

Sheet
E

25

of

36

+3VALW TO +3VS

+1.5V TO +1.5VS
+1.5V

Q4A
Q4B
SUSP
2
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6

C420
1.5V@

R320
820K_0402_5%
1.5V@

1.5V@
2 R315
1
+VSB
100K_0402_5%

3 1

1U_0402_6.3V4Z
+1.5VS_GATE

1.5V@
R314
470_0603_5%

C413

Q8A 1.5V@
SUSP
2
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6

Q8B
1.5V@

R319

C421
1.5V@

1.5V@

0.1U_0603_25V7K

C419

1.5V@

1
2
3
4

S
S
S
G

AO4468_SO8

1 R317
2
+VSB
220K_0402_5%

3 1

1U_0402_6.3V4Z
+3VS_GATE

R313
470_0603_5%

D
D
D
D

C412

8
7
6
5
4.7U_0805_10V4Z

C418

Q22 1.5V@

1
4.7U_0805_10V4Z

Q5B
SUSP
2
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6

AO4468_SO8

Q5A

1
2
3
4

1 R316
2
+VSB
220K_0402_5%

S
S
S
G

C411

C417

R312
470_0603_5%

D
D
D
D

C410

4.7U_0805_10V4Z

8
7
6
5

+5VS_GATE
R318

4.7U_0805_10V4Z

C416

0.01U_0402_25V7K

4.7U_0805_10V4Z

AO4468_SO8

3 1

1U_0402_6.3V4Z

+1.5VS

+3VS

Q21

1
2
3
4

S
S
S
G

D
D
D
D

C408

820K_0402_5%

8
7
6
5

4.7U_0805_10V4Z
1
C409

Q20

+3VALW

820K_0402_5%

+5VS

0.022U_0402_25V7K

+5VALW

+5VALW TO +5VS

+1.1VALW TO +1.1VS
+1.1VALW

+1.1VS

+5VALW

+5VALW

U18

R321

R356 @
100K_0402_5%

R323
100K_0402_5%

470_0603_5%
+1.1VS_ON#

SUSP

SUSP

<33>

2
1U_0603_10V4Z

2
C422

IRF8113PBF_SO8

1
2
3

8
7
6
5

2N7002DW-T/R7_SOT363-6

Q29 @
S 2N7002W-T/R7_SOT323-3

Q30
S 2N7002W-T/R7_SOT323-3

2
G

<17,23,30,33> SUSP#

@R362
@
R362

R327

10K_0402_5%

10K_0402_5%

0.1U_0603_25V7K

C423

2
1

2
G

2
4

820K_0402_5%

3
Q6B
+1.1VSON# 5
2N7002DW-T/R7_SOT363-6

R325

+1.1VSON
+1.1VSON#

+1.1VS_GATE

1 R324
2
220K_0402_5%

Q6A
+VSB

DISCHARGE

@R250
@
R250 2

R332
470_0603_5%

+1.1VS_ON <23>

+1.8VS_PG <30>

2
G

SUSP

SUSP

2
G

Q26

2N7002W-T/R7_SOT323-3

2N7002W-T/R7_SOT323-3

2
G

Q27

SUSP

1
R328

2
0_0402_5%

D
Q24

NC7SZ08P5X_NL_SC70-5
U23 @

+1.1VSON

R331
470_0603_5%

R329
470_0603_5%

+3VS
@
C361 0.1U_0402_16V7K
1
2

+1.8VS

+0.75VS

+1.0VS

1 0_0402_5%

2N7002W-T/R7_SOT323-3

+1.1VSON#
1
@R295
@
R295

+1.1VS_ON#
2
0_0402_5%

+1.1VSON#

2
0_0402_5%

1
R301

SUSP

2009/02/04

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/02/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

DC Interface
Size Document Number
Custom

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC

Date:

Friday, December 03, 2010

Sheet
E

26

of

36

PL1
HCB2012KF-121T50_0805
1
2

1
2

X7R type

PU1

VCC TMSNS1

GND RHYST1

OT1 TMSNS2

OT2 RHYST2

OTP_N_001
OTP_N_002

1
PR2

9.53K_0402_1%

PL3
HCB2012KF-121T50_0805
1
2

G718TM1U_SOT23-8

VMB

+3VALW

PH1
100K_0402_1%_NCP15WF104F03RC

EN0

<29>

1
PR4

VS_ON

<29>

If EC use 3VL and can not detect VGATE,


must connect EN0

0_0402_5%

@PR27
@
PR27
100K_0402_1%

+3VALW

2
BATT+

PC6
1000P_0402_50V7K

TS_A
EC_SMDA
EC_SMCA
GND

PR28

1
ID
BI

PC7
0.01U_0402_25V7K

Install when EC use +3VL


and SUSP was Pull high to +3VL.

PJP1

PD1

Reserve when EC use +3VALW.

PJ1

PR92
1K_0402_1%

PR95
1K_0402_1%
1
2

@ 100K_0402_1%

G2
G1
9
8
7
6
5
4
3
2
1

11
10
9
8
7
6
5
4
3
2
1

1
PR3 @ 0_0402_5%

PL4
HCB2012KF-121T50_0805
1
2

SUYIN_200275GR009G17NZR_9P-T

need confirm: ME give us battery


connector P/N is DC040006H00

OTP_N_003

PR1
21K_0402_1%

1
PC5
0.1U_0603_16V7K

PC4
100P_0402_50V8J

1
2

VL
PC3
1000P_0402_50V7K

2 2
1 1
PJPDC1

TARNG_TB3061HNR-02

PC1
1000P_0402_50V7K

PH1 under CPU botten side :


CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C

VIN

PL2
HCB2012KF-121T50_0805
1
2

ADPIN

PC2
100P_0402_50V8J

P/N:DC30100CB00

JUMP_43X39

EC_SMB_DA1 <23>

VL

1
2
PQ1
TP0610K-T1-E3_SOT23-3

VSB_N_001

PQ2
SSM3K7002FU_SC70-3
3

Reserve when EC use +3VL.


Install when EC use +3VALW.

VIN

1VSB_N_003

PR16
0_0402_5%
2VSB_N_002 2
G
PC10
0.1U_0402_16V7K

<29,32> POK

2
1

PR13
100K_0402_1%

PR12
22K_0402_1%
1
2

EC_SMB_CK1 <23>

BATT_TEMP <23>

@ PJSOT24CW_SOT323-3

+VSBP

1
PC9
0.1U_0603_25V7K

B+

PC8
0.22U_0603_25V7K

+3VALW

PR91
6.49K_0402_1%

2
1
PR96
100_0402_1%

PR93
100_0402_1%
1
PR94
1K_0402_1%

1
PD2

2
1
PR10
100K_0402_1%

@ PJSOT24CW_SOT323-3

PD3
RLS4148_LL34-2
VS_N_001
1

+VSB

(120mA,40mils ,Via NO.= 1)

PR18
68_1206_5%

VS

<24>

2
PR22
22K_0402_1%

51_ON#

PC12
0.1U_0603_25V7K

PC11
0.22U_0603_25V7K

PR21
100K_0402_1%

JUMP_43X39

PQ3
PR17
TP0610K-T1-E3_SOT23-3 68_1206_5%
N1

PD4
RLS4148_LL34-2

BATT+

PJ2
+VSBP

VS_N_002
4

Reserve when EC use +3VL.


Install when EC use +3VALW.

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/01/23

Deciphered Date

2010/01/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

DCIN / BATT CONN / OTP


Size

Document Number

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC


Date:

Friday, December 03, 2010

Sheet

27

of

36

PL403
1.2UH +-30% 1231AS-H-1R2N=P3 2.9A
1
2

VCOMP

CSIP

19

ICM

PHASE

18

VREF

UGATE

17

CHLIM

BOOT

16

PC106
2200P_0402_25V7K

2
1CHG_N_008
1
1

5
10

ACLIM

VDDP

PQ110

DH_CHG
PR126
0_0603_5%
BST_CHG 1
2

PC121
0.1U_0603_25V7K
BST_CHGA 2
1

6251VDDP

15

11

VADJ

LGATE

14

12

GND

PGND

13

DL_CHG

PD106
RB751V-40_SOD323-2
1

26251VDD

AON7406L_DFN8-5

PR129
4.7_0603_5%
PC123
4.7U_0805_6.3V6K

ISL6251AHAZ-T_QSOP24

PR102
0.02_1206_1%
4

BATT+

PR105
18.2K_0402_1%
1
2

2
PL101
8.2UH_PCMB063T-8R2MS_4.5A_20%
CHG
1
2

3
2
1

PR122
2.2_0603_1%

LX_CHG

CHG_N_001
4

10U_0805_25V6K
PC102

20

2ACPRN
G
PQ109 @
SSM3K7002FU_SC70-3

10U_0805_25V6K
PC101

CSIN

ICOMP

@ PC114
2
1

CSOP

21

PR125
4.7_1206_5%

CSOP

CELLS

PR130
100K_0402_1%

AON7408L_DFN8-5

CHG_SNUB 2

226K_0402_1%
PR128
20K_0402_1%

PR111
14.3K_0402_1%

2
DCIN

VIN

PQ108

CSON

6251aclim

PR118
20_0603_5%
CHG_CSON 1
2
PC113
0.047U_0603_16V7K
CHG_CSOP 1
2
PR119
20_0603_5%
CHG_CSIN
2
1
PC118
PR120
0.1U_0603_25V7K 20_0603_5%
CHG_CSIP
1
2
2

22

PD101

EN

6251VREF 1
Rtop PR127

<23> CHGVADJ

PQ106
DTC115EUA_SC70-3

ACPRN

PR104
140K_0402_1%

23

CSON

PR110
47K_0402_1%
1
2

PC124
@ 680P_0603_50V7K

PQ111
DTC115EUA_SC70-3

ACSET ACPRN

CHG_N_005

3
2
1

ACOFF

8
7
6
5

PR112
10K_0402_1%

PC112
1U_0603_25V6K
1
2

ACOFF

<23>

24

IREF

ADP_I

<23>

PR103
<23>
150K_0402_1%
2
1

PC122
0.01U_0402_25V7K
2
1

PC120 must close EC pin.

CHG_VCOMP

PR123 47K_0402_1%
1
2CHG_ICM
PC119 @ 100P_0402_50V8J
1
2
6251VREF
PC120
0.1U_0402_16V7K
CHG_CHLIM
1

DCIN

0.01U_0402_25V7K

VDD

PR124
22K_0402_5%
PACIN 1
2

6.81K_0402_1%
2

CHG_VADJ

6800P_0402_25V7K
CHG_ICOMP
2

10_1206_5%

2
PC116
1
PC117
PR121
1
2CHG_VCOMP1 1

6251VDD

PD104
@ GLZ27D_LL34-2
1
2

CHG_N_009

CSON

6251_EN

@PC115
@
PC115
680P_0402_50V7K
1
2

ACSETIN

PC110
1000P_0402_25V8J

PR113

PU101

PQ107B
SSM6N7002FU-2N_SOT363-6

3CHG_N_002

SSM6N7002FU-2N_SOT363-6

RB751V-40_SOD323-2
CHG_VIN 1
2

PC109
2.2U_0603_6.3V6K
2
1

ACSETIN

@PC111
@
PC111
0.1U_0402_16V7K

CHG_N_001

<23> FSTCHG
PR116
150K_0402_1%

PR114
10K_0402_1%
2
1

PR117
100K_0402_1%

@PD103
@
PD103
1SS355_SOD323-2
1
2

PQ107A
2

PC107
5600P_0402_25V7K
1
2

6251VDD

CHG_N_003

PQ105
DTC115EUA_SC70-3

PR108
191K_0402_1%
1
2

1
2

PC108
0.1U_0603_25V7K

CSIN

CSIP

PR107
200K_0402_1%

PR109
47K_0402_1%

1CHG_N_010

PQ104
DTA144EUA_SC70-3

PQ103
AO4435L_SO8
1
2
3

VIN

8
7
6
5

B+
CHG_B+

@PL102
@
PL102
HCB2012KF-121T50_0805
1
2

PC105
0.1U_0402_25V6
2
1

1
2
3

B+

PR101
0.02_1206_1%
1
4

PC104
4.7U_0805_25V6-K
2
1

1
2
3

8
7
6
5

P3

VIN

PQ102
AO4409_SO8

10U_0805_25V6K
PC103

P2

PQ101
AO4435L_SO8

0.1U_0603_25V7K

PR106
31.6K_0402_1%

6251VDD

PR131
47K_0402_1%

<23>

ACPRN

Iada=0~3.421A(65W);CP=2.91A;

PQ112

2
B

CP= 85%*Iada;

ACIN
PACIN

PR132
10K_0402_1%

PR133
10K_0402_1%
1
2

PR136
20K_0402_1%

Add

E
MMBT3904W_SOT323-3

CP mode
Vaclim=VREF*(Rbot//Rinternal/(Rtop//Rinternal+Rbot//Rinternal))
65W Vaclim=2.39*(20K//152K/(20K//152K+226K//152K))=0.38914V
Iinput=(1/Racdet)*((0.05*Vaclim/VREF+0.05))
65W,Iinput=(1/0.02)*(0.05*0.38914/2.39+0.05)=2.92A

CHGVADJ=(Vcell-4)/0.10627

CC=0.25A~3A
IREF=1.016*Icharge

Vcell

IREF=0.254V~3.048V

4V

VCHLIM need over 95mV

4.2V

CHGVADJ
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

0V
1.882V

2009/01/23

Deciphered Date

2010/01/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

CHARGER
Size

Document Number

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC


Date:

Friday, December 03, 2010


D

Sheet

28

of

36

PC308
1U_0603_16V6K
2
1

2VREF_51125

PR301
13.7K_0402_1%
1

PL301
HCB2012KF-121T50_0805

FB_3V

FB_5V

PR305
30.9K_0402_1%
2

PR306
20K_0402_1%
2

B++

ENTRIP2

19

LG_5V

5
3
2
1
5
6
7
8

PC318
4.7U_0805_10V6K

+5VALWP

1
+

PC305
150U_B2_6.3VM_R35M

+5VALWP
Imax=4A
Ipeak=5.2A
Iocp(minimum)=6.5A

B++

AO4468L_SO8

VL

2VREF_51125

PC307
10U_0805_25V6K

1
2

RT8205EGQW_WQFN24_4X4

EN0

PC320
@ 1U_0603_10V6K

<27,32>
PQ306

18

17

POK

16

@ PC306
4.7U_0805_25V6-K

VCLK

VREG5

VIN

GND

EN0

PR314
499K_0402_1%
2

PL305
4.7UH_PCMC063T-4R7MN_5.5A_20%
2
1

PC317
680P_0603_50V7K

DRVL1

DRVL2

PR313
4.7_1206_5%
2
1

LX_5V

12

4
PR309
PC315
2.2_0402_5%
0.1U_0402_10V7K
BST_5V 1
2 BST1_5V 1
2

SNUB_5V

UG_5V

20

LL2

PQ305
AON7408L_DFN8-5

21

LL1

11

3
2
1

22

DRVH1

PC312
2200P_0402_50V7K
2
1

ENTRIP1

VFB1

VBST1

DRVH2

PC319
0.1U_0603_25V7K

6ENTRIP1

VREF

VBST2

PQ307A

PQ307B
N_3_5V_001

5
4

SSM6N7002FU-2N_SOT363-6

SSM6N7002FU-2N_SOT363-6

PJP305

+5VALWP

PR317
100K_0402_5%

@PR318
@
PR318
100K_0402_1%
1
2

<17,23,24> EC_ON

TONSEL

23

<27>

24

1
2
3

AO4468L_SO8

VFB2

VO1

VREG3

13

PR311
100K_0402_1%
2
1

B++

PR307
110K_0402_1%
2

PGOOD

VO2

15

8
7
6
5

LG_3V

SNUB_3V

1
PC303
220U_6.3V_M

LX_3V
PQ304

PC316
@ 680P_0603_50V7K

+3VALWP

PR312
@ 4.7_1206_5%

PL303
4.7UH_PCMC063T-4R7MN_5.5A_20%
2
1

PC311
0.1U_0402_25V6
2
1

ENTRIP2

1
2
3

PC314
8
0.1U_0402_10V7K
PR308
BST1_3V 1
1
2
2BST_3V 9
0_0402_5%
UG_3V
10

SKIPSEL

+3VALWP
Imax=3A
Ipeak=3.8A
Iocp(minimum)=5A

P PAD

25

ENTRIP2

PU301

PC313
10U_0805_6.3V6M

14

1
2

PC304
4.7U_0805_25V6-K

PC310
2200P_0402_50V7K
2
1

PR303
102K_0402_1%
1
2

PQ303
AON7408L_DFN8-5

ENTRIP1

+3VLP

2
PC309
0.1U_0402_25V6
2
1

PR302
20K_0402_1%
1
2

B++

B+

+5VALW

(4A,160mils ,Via NO.= 8)

+3VALW

(3A,120mils ,Via NO.= 6)

PAD-OPEN 4x4m
PJP303

VL
1

+3VALWP

2
PAD-OPEN 4x4m

PQ308
DTC115EUA_SC70-3

VS_ON

+3VL

+3VLP
PJP302

PR319
100K_0402_1%

2
PC321
@ 0.01U_0402_16V7K

2
2
1
PR320
40.2K_0402_1%

<27>

VS

1
PAD-OPEN 2x2m
4

EC:+3VL, reserve PR319, install PR318, PR320 100K


EC:+3VALW, reserve PR318, install PR319, PR320 40.2K

Compal Secret Data

Security Classification

2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.


3.3VALWP/5VALWP

Size Document Number


Custom

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC

Date:

Friday, December 03, 2010

Sheet
E

29

of

36

+3VALW

PR406
100K_0402_1%

+1.8VS_PG <26>

<Vo=1.8V> VFB=0.6V
Vo=VFB*(1+PR401/PR402)=0.6*(1+20K/10K)=1.8V

1
PR402
10K_0402_1%

1
2

PC402
22U_0805_6.3VAM

PC401
22U_0805_6.3VAM

68P_0402_50V8J
PC404

+1.8VSP

SY8033BDBC_DFN10_3X3

PR401
20K_0402_1%
2

1
1.8VSP_FB

PR403
4.7_1206_5%

NC

TP

FB

11

EN_1.8VSP

47K_0402_1%
PR405
1M_0402_5%

PC405
2200P_0402_25V7K

1
PR404

<17,23,26,33> SUSP#

EN

LX

SVIN

SNUB_1.8VSP

PVIN

8
5

PL401
1UH_MMD-06CZ-1R0M-V1_11A_20%
1
2

1.8VSP_LX

PC406
680P_0603_50V7K

LX

NC

PVIN

PC403
22U_0805_6.3VAM

10

1.8VSP_VIN

PU401

HCB1608KF-121T30_0603
1
2

PG

PL402
+5VALW

PJP401
+1.8VSP

+1.8VS

(2A, 80mils, Via NO.= 4)

PAD-OPEN 3x3m
3

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/01/23

Deciphered Date

2010/01/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

+1.8VSP
Size

Document Number

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC


Date:

Friday, December 03, 2010


D

Sheet

30

of

36

1.5V_B+

PGOOD

NC

3
2
1

BOOT

12

CS

11

TRIP_1.5V 1

VDDP

10

1
@PR517
@
PR517

LGATE

100K_0402_1%

LG_1.5V

15K_0402_1%
2

PQ502
IRF8707GTRPBF_SO8

+5VALW
PC510
4.7U_0805_10V6K

RT8209BGQW_WQFN14_3P5X3P5

PR501

1
2

1
2

10U_0805_25V6K
PC503

2200P_0402_50V7K
PC506

+
2

PC511
@ 680P_0603_50V7K

+1.5VP_PWRGD

PR509 @
4.7_1206_5%

3
2
1

PR508
+5VALW

PGND

+3VALW

+1.5VP

PL501
2.2UH_MMD-06CZ-2R2M-V1_8A_20%
1
2

PC501

PHASE

LX_1.5V

PQ501
AON7408L_DFN8-5

220U_6.3V_M

FB

14

UG_1.5V

VDD

5
6
7
8

VOUT

13

UGATE

PC509
4.7U_0603_6.3V6M

TON

GND

PR507
100_0603_1%

2
0_0402_5%
V5FILT_1.5V

PC508
0.1U_0402_10V7K

1
PR505

+1.5VP
+5VALW1

VOUT_1.5V

EN/DEM

PU501

15

PR504
0_0402_5%
BST_1.5V 1
2BST1_1.5V

+5VALW

@ PC504
4.7U_0805_25V6-K

0_0402_5% PC505
@ 0.1U_0402_10V7K

PR506
255K_0402_1%
1
2TON_1.5V

B+

PL502
HCB1608KF-121T30_0603
2
1

EN_1.5V

SYSON

1SNUB_1.5V
2

<23>

PC507
0.1U_0402_25V6

PR503
D

2.21K_0402_1%

2
1
2
1

1
2

1.35V@ PR512
100K_0402_1%

1.35V@ PC512
0.01U_0402_25V7K

DDR_VID

<13>
B

1.35V@PR513
10K_0402_5%

1.35V@ PR514
100K_0402_1%

+1.5VP
Imax=6.5A
Ipeak=9A
Iocp(minimum)=10.2A

+3VALW

2
3

1
2

1.35V@PR511
4.7K_0402_5%
2
1
1.35V@ PC502
0.1U_0402_16V7K

1.35V@ PQ504
2N7002W-T/R7_SOT323-3

2
G

1
1

1.35V@ PQ503
PMBT2222A_SOT23-3

1
PR502
2.15K_0402_1%

1.35V@ PR515
180K_0402_1%

+3VALW
PR516 1.35V@
162K_0402_1%

PJP501
1

+1.5VP

+1.5V

(6.5A,260mils ,Via NO.= 13)

PAD-OPEN 4x4m

Voltage Select
DDR_VID

DDR voltage

+1.5V

+1.35V

Compal Secret Data

Security Classification

2007/05/29

Issued Date

Deciphered Date

2008/05/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


+1.5VP

Size

Document Number

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC


Date:

Friday, December 03, 2010

Sheet
1

31

of

36

1.1V_B+

FB_1.1V
6

PR702
10K_0402_1%

3
2
1

BOOT

NC

14

PGOOD

13

UG_1.1V

PHASE

12

LX_1.1V
TRIP_1.1V 1

CS

11

VDDP

10

LGATE

PR708
+5VALW
LG_1.1V

15K_0402_1%
2
+5VALW

1
2

2200P_0402_50V7K
PC705

PC701
220U_6.3V_M

FDS6690AS-G_SO8
4

RT8209BGQW_WQFN14_3P5X3P5

+1.1VALWP
C

PR709
@ 4.7_1206_5%

PQ702

PC709
4.7U_0805_10V6K

3
2
1

2
2
PR710
100K_0402_1%

@ PC703
4.7U_0805_25V6-K

10U_0805_25V6K
PC702

PL701
1UH_MMD-06CZ-1R0M-V1_11A_20%
1
2

FB

UGATE

PQ701
AON7408L_DFN8-5

5
6
7
8

VDD

1SNUB_1.1V 2

4.64K_0402_1%

PC707
0.1U_0402_10V7K

+1.1VALWP

PR701

PC708
4.7U_0603_6.3V6M

VOUT

PGND

TON

PR707
100_0603_1%

+5VALW1

+5VALW

+1.1VALWP

VOUT_1.1V

2
0_0402_5%
V5FILT_1.1V

EN/DEM

GND

PR705
255K_0402_1%
1
2TON_1.1V

15

PR704
0_0402_5%
BST_1.1V 1
2BST1_1.1V

1
PR706

0_0402_5% PC704 @
0.1U_0402_10V7K

PU701

B+

PL702
HCB1608KF-121T30_0603
2
1

EN_1.1V

POK

PC706
0.1U_0402_25V6

PR703
<27,29>

+3VALW 1

+1.1VALWP
Imax=7A
Ipeak=9.93A
Iocp(minimum)=11.3A

PC710
@ 680P_0603_50V7K

+1.1VAlwP_PWRGD

+
2

PJP701
+1.1VALWP

+1.1VALW

(7A,280mils ,Via NO.=14)

PAD-OPEN 4x4m

Compal Secret Data

Security Classification

2007/05/29

Issued Date

Deciphered Date

2008/05/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


+1.1VALWP

Size

Document Number

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC


Date:

Friday, December 03, 2010

Sheet
1

32

of

36

+1.5V

VCNTL

GND

NC

VREF

NC

VOUT

NC

TP

+3VALW

+1.1VALW

4
1

+VSB

PR605
330K_0402_5%

PQ603
2
G

double check sequence


SUSP

PC606
0.1U_0402_10V7K

PC608
4.7U_0603_6.3V6K

PR603
1
2
47K_0402_5%

PC609
4.7U_0603_6.3V6K

PC602
1U_0402_6.3V6K

1
PC605
10U_0805_6.3V6M

1
2
3

8
7
6
5

+0.75VSP

PR602
1K_0402_1%

2
1
PC604
0.1U_0402_16V7K

1
S

1
3

SUSP

<26>

PQ601
IRF8707GTRPBF_SO8

G2992F1U_SO8
VREF_G2992
PQ602
SSM3K7002FU_SC70-3
PR604
10K_0402_1%
1
20.75VS_N_002
2
G

Follow HW request 1.0V change to 1.05V 0824

+1.0VSP

+1.1VALW TO +1.0VSP
PC603
1U_0603_10V6K

PC607
0.1U_0402_25V6

PR601
1K_0402_1%

PC601
4.7U_0805_6.3V6K

VIN

2
1

PU601

SSM3K7002FU_SC70-3

PJP601

+0.75VSP

+0.75VS

PJP602

(2A,80mils ,Via NO.= 4)


1

+1.0VSP
PAD-OPEN 3x3m

+1.0VS

(5A,200mils ,Via NO.= 10)

PAD-OPEN 4x4m

Follow HW request 1.0V change to 1.05V 0824

+5VALW
+5VALW

Reserve 1.0VSP backup solution

For low power DDR 1.35V, WLAN need 1.5V support

@
APL5930KAI-TRG_SO8

<17,23,26,30> SUSP#

1
2
@PR615
@
PR615
0_0402_5%

+3VS

1.5VS_FB

2
1.0VSP_POK

@PR617
@
PR617
10K_0402_5%

PR614

PC618
@22U_0805_6.3V6M

@PR616
@
PR616
31.6K_0402_1%

@ PR612
@PR612
39.2K_0402_1%

+3VS

FB

APL5916KAI-TRL_SO8

+1.0VP
2

3
4
PC622
2
1

VOUT
VOUT

PR611
10K_0402_1%
2
1

EN
POK

@PC621
@
PC621
0.1U_0402_10V7K

8
7

PC617 @
22U_0805_6.3V6M

VCNTL
VIN
VIN
GND

1
2

1.5VSP_EN

6
5
9

33P_0402_50V8J

@ PC619
@PC619
10U_0805_10V6K

1
2
@ PR613
0_0402_5%

1.5VS_FB

+1.5VSP
2

PC616
2
1

FB

@ 47P_0402_50V8J

3
4

EN
POK

VOUT
VOUT

<17,23,26,30> SUSP#

8
7

@ PC615
@PC615
0.1U_0402_10V7K

VCNTL
VIN
VIN

PR610
10K_0402_1%
2
1

1.5VSP_EN

@ PC614
@PC614
10U_0805_10V6K

6
5
9

GND

FB=0.8V
PU604 @

PU603

+1.8VSP
@PC613
@
PC613
1U_0603_10V6K

+1.1VALW @
@PC620
PC620
1U_0603_10V6K

1.5VS_POK

@ 10K_0402_5%
PJP604
+1.0VP

PJP603
+1.5VSP

+1.0VS

(5A,200mils ,Via NO.= 10)

PAD-OPEN 4x4m

+1.5VS

(2A,120mils ,Via NO.= 4)

PAD-OPEN 3x3m
A

Compal Secret Data

Security Classification

Issued Date

2006/11/23

Deciphered Date

2007/11/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


0.75VSP

Size

Document Number

Rev
0.1

PCM10 LA6741 M/B SCHEMATIC


Date:

Friday, December 03, 2010

Sheet
1

33

of

36

CPU_B+

PWROK

UGATE0

34

UGATE0

SVD

PHASE0

33

PHASE0

CPU_SVC1

SVC

PGND0

32

LGATE0

31

PVCC

30

LGATE1

29

OCSET

VDIFF0

PGND1

28

PHASE1

27

UGATE1

26

BOOT1

25

2.2_0603_5%

@
PC209

PC208
@
68U_25V_M_R0.44

68U_25V_M_R0.44

PC213
2200P_0402_50V7K
2
1

PC212
0.1U_0402_25V6
2
1

PC220
2200P_0402_50V7K
2
1

PC219
0.1U_0402_25V6
2
1

3
2
1

PL201
0.47UH_MMD-06CZ-R47M-V1_17.5A_20%
1
2
+CPU_CORE

PC221
0.22U_0603_10V7K

PQ202
AO4726L_SO8

+5VS

PR219
@ 4.7_1206_5%

LGATE0

PC224
1U_0603_10V6K

PR222
10.7K_0402_1%

PC223
@ 680P_0603_50V7K

PC222
2
1
0.1U_0603_16V7K

LGATE0

ISP0

PR225
1.30K_0402_1%

TP

ISN1

ISP1

VW1

COMP1

FB1

VDIFF1

BOOT0_1
1

<5> VDDCR_APU_SENSE_L

49

24

23

22

21

20

19

18

17

16

15

14

+CPU_CORE
Imax=7.7A
Ipeak=11A
Iocp(minimum)=13.2A

ISN0

<5> VDDCR_APU_SENSE_H

ISP0
ISN0
PR226
0_0402_5%
2
1 VSEN0
0_0402_5%
2 PR227 1 RTN0

ISP0

10_0402_5%

RTN1

@PR236
@
PR236

@ PR228
1K_0402_1%
1
2

10_0402_5%

+5VS

PR237
1K_0402_1%
1
2

@PR235
@
PR235
3

13

ISP0

+CPU_CORE

VSEN1

VW0

RTN1

COMP0

12

RTN0

11

VSEN0

FB0

ISN0

10

10U_0805_25V6K
PC202

@ PC201
4.7U_0805_25V6-K
2
1

BOOT0 1 PR218

ISN0

CPU_SVD1

BOOT0

CPU_OCSET

35

ISL6265CHRTZ-T_TQFN48_6X6

CPU_B+

36

BOOT0

RBIAS

@ PC207
4.7U_0805_25V6-K
2
1

1
PC217
@ 680P_0603_50V7K

5
6
7
8

38

39

BOOT_NB

PGOOD

ENABLE

+CPU_CORE_NB
Imax=7A
Ipeak=10A
Iocp(minimum)=12A

220U_D2_2VY_R15M

37
UGATE_NB

PHASE_NB

40
PGND_NB

LGATE_NB

41
OCSET_NB

43

42
RTN_NB

44

45

46

47

OFS/VFIXEN

UGATE0_1

PHASE0
BOOT_NB

CPU_RBIAS

PC205

1SNUB_CPU2

2 PR220 1
0_0402_5%
2
1
PR221
0_0402_5%

1
+

RTN_NB

COMP_NB

FSET_NB

FB_NB

VSEN_NB

PQ201
AON7408L_DFN8-5
PR214
0_0603_5%
1
2

B+

+CPU_CORE_NB

LGATE_NB
PHASE_NB

PR224
95.3K_0402_1%
2
1

<5>

PR223
21.5K_0402_1%
2
1

1
VDDCR_NB_SENSE_L
PR208
@PR234
@
PR234
0_0402_5% 10_0402_5%
1
2
PR209
42.2K_0402_1%
PHASE_NB
1
2

PR205
@ 4.7_1206_5%

3
2
1

<23> VR_ON_EC

<5>

6265A_PWROK

<5> APU_SVD
<5> APU_SVC

VSEN_NB

2
PR216 0_0402_5%

FSET_NB

2
PR217 @ 0_0402_5%

FB_NB

COMP_NB

VIN

PU201

2
<15> FCH_PWROK
<14> APU_PWRGD_CORE

VDDCR_NB_SENSE_H

UGATE0
PR215
@ 105K_0402_1%

<15,23> VGATE

UGATE_NB

VCC

6265A_OFS
PR213
@ 10K_0402_1%

PL202
1UH_MMD-06CZ-1R0M-V1_11A_20%
1
2

PC216
0.22U_0603_10V7K
4

PR212
@ 105K_0402_1%

@PR233
@
PR233
10_0402_5%
2+CPU_CORE_NB
LGATE_NB

1
2

1
PR211
0_0402_5%

1
2

2
2

PC218
0.1U_0603_25V7K

48

1
PR210
10K_0402_1%

PR206
2_0603_5%

+3VS

+5VS

2
6265A_VIN

CPU_B+

PR207
0_0402_5%
2
1

PHASE_NB
PR204
2.2_0603_5%
BOOT_NB 1
2BOOT_NB11

PQ204
AO4468L_SO8

PR203
22K_0402_1%
2
1

3
2
1

PC214
1000P_0402_50V7K
2
1

PC215
0.1U_0603_16V7K

UGATE_NB

OCSET_NB

+5VS

PC211
1000P_0402_50V7K

5
6
7
8

PR202
44.2K_0402_1%
PR201
2_0603_5%
1
26265A_VCC

PQ203
AON7408L_DFN8-5

1SNUB_CPUNB
2

FB1_NB 2

3
2
1

PC210
33P_0402_50V8J
2
1

10U_0805_25V6K
PC203

PL203
HCB2012KF-121T50_0805
2
1

+1.5VS

DIFF_0

VW0

PR229
PC225
255_0402_1%
4700P_0402_25V7K
FB_0
2
1FB_0_2 2
1

COMP0

PC226
180P_0402_50V8J
4

PR230
1K_0402_5%
2
1

PR231

2
54.9K_0402_1%

PC228
FB_0_1 2
1

PC227
1000P_0402_50V7K
4

PR232
6.81K_0402_1%
2
1

1200P_0402_50V7K

Compal Secret Data

Security Classification

2008/9/25

Issued Date

2009/9/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.


+CPU_CORE

Size Document Number


Custom

Rev
0.2

PCM10 LA6741 M/B SCHEMATIC

Date:

Friday, December 03, 2010

Sheet
E

34

of

36

Version Change List ( P. I. R. List ) for Power Circuit


Item Page#
D

34

29

Reason for change

phase

Description

change CPU_CORE input CAP to 68U for height issue.


Change 3/5V IC to TPS51125 for business issue.

29

33

Change 0.75V IC to G2992 for business issue.

33

Change PC607 to 0.1U for HW sequence issue.

for common design

change CPU_CORE input CAP.

modify
delete: PC208/PC209 SF000000I80
add: PC208/PC209 SF000000Y00

DVT
DVT

Change 3/5V IC to TPS51125


3/5V PIN25 can't contact to GND
and change PR315 to 100K

DVT

Change 0.75V IC to G2992

DVT

Change PC607 from 0.01U change to 0.1U

Rev.
D

Change 3/5V IC from UP6182 change to TPS51125


3/5V PIN25 can't contact to GND and change PR315 to 100K
Change 0.75V IC from UP7711 change to G2992

DVT

from SE075103K80 change to SE00000G880

Change PR604 from 0 to 10K,and PC606


change to 0.1U for RC delay.
Change PR404 from 0ohm to 47K and
PC405 from @ to 2200P
Delete: PD102,PD103,PD105,PR115,PC111,
PC114,PQ109. Add: PR130

Change PR604 from 0ohm to 10K,and PC606 from @


change to 0.1U
Change PR404 from 0ohm to 47K and
PC405 from @ to 2200P
Delete: PD102,PD103,PD105,PR115,PC111,
PC114,PQ109. Add: PR130

DVT

Change PR616 from 39.2K change to 31.6K

DVT

Change PR616 from 39.2K change to 31.6K

DVT

Change DC-Cable P/N:DC30100CB00

33

Change PR604 and PC606 for HW sequence issue.

30

Change PR404 and PC405 for HW sequence issue.

28

33

10

27

11

29

Cost down

PC305 change to B2 size

DVT

PC305 P/N from SG020151330 change to SGA00002N80

12

32

Cost down

change PC701 for cost down.

DVT

PC701 P/N from SGA00004L00 change to SF000002N00

13

29

Cost down

5V low-side change to AO4468L

DVT

PQ306 P/N from SB00000E310 change to SB000009510

14

28

CC-CV mode voltage is abnormal

DVT

PU101 P/N from SA00003TK00 change to SA00001EP80

15

29

due to change 5V L-side MOS and


3/5V OCP resister,

DVT

PR303 change to 102K, PR307 change to 65.5K

DVT

PR508 from 15.4K change to 15K

DVT

PR708 from 16.5K change to 15K

change CPU_CORE_NB L-side MOS and


CORE_NB OCP resister,

DVT

PL202 from 2.2U change to 1U

change CPU_CORE NB L-side MOS

DVT

16

for common design


for AMD request 1.0V change to 1.05V
follow PBL00/01 DC- cable

32

18

34

19

34

20

34

charge IC form G5209 change to ISL6251


change 3/5V OCP resister,

due to change 1.5V L-side MOS and


1.5V OCP resister,
due to change 1.1V L-side MOS and
1.1V OCP resister,

31

17

Change DC-Cable P/N:DC30100CB00

change 1.5V OCP resister,

DVT

for cost down change CPU_CORE NB L-side MOS

CPU_CORE_NB L-side MOS from FDS6690 change to AO4468L

delete PC208 and PC209 for cost down

delete PC208 and PC209

DVT

For DVT phase material short, change P/N

change PC205, PC303, PC501, PC701

PVT

P/N from SF000002N00 change to SF000003I00

delete 1.0V LDO for cost down.

delete 1.0V LDO

PVT

delete 1.0V LDO

22

33

24

34

for common design

25

29

modify 5V_alw OCP

change 1.1V OCP resister,

for cost down change CPU_CORE NB L-side MOS


and CORE_NB OCP resister,

21

DVT

PIN17 RTN1 net from 5VS change to 1.5V


change PR307 from 65.5K to 86.6K

delete PC208 and PC209

PVT

PIN17 RTN1 net from 5VS change to 1.5V

PVT

P/N change to SD034866280

Security Classification

Issued Date

Compal Secret Data


Title

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Compal Electronics, Inc.


Power Changed-List History-1

Size Document Number


Custom
Date:

Rev
1.0

Friday, November 26, 2010

Sheet
1

35

of

36

Version Change List ( P. I. R. List ) for Power Circuit


Item Page#
D

28

28

33

Reason for change


Change charge bead to choke for EMI request.

29

34

34

add PL403 (SH00000IY00)

for common design

phase

Description

modify

Rev.

delete: PL102
add: PL403

Pre-MP

Change charge input CAP from 10U to 4.7U

Pre-MP

Change charge input CAP PC104 from 10U to 4.7U

PQ601 A04712 maybe cause leakage issue.

Change PQ601 from AO4712 to IRF8707

Pre-MP

Change PQ601 from AO4712 to IRF8707

For DVT phase material short, change P/N

change PC205, PC303, PC501, PC701

Pre-MP

P/N from SF000003I00 change to SF000003000

change PR307 from 86.6K to 110K

Pre-MP

P/N change to SD034110380

change PC205 to D2 size

Pre-MP

change PC205 to D2 size, P/N change to SGA00004L00

modify 5V_alw OCP


change PC205 to D2 size to meet ME request
for common design

PIN17 RTN1 net from 5VS change to 1.5Vs

PVT

PIN17 RTN1 net from 5VS change to 1.5Vs

8
C

9
10
11
12
13
14
15
16
B

17
18
19
20
21
22
24
A

25

Security Classification

Issued Date

Compal Secret Data


Title

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Compal Electronics, Inc.


Power Changed-List History-1

Size Document Number


Custom
Date:

Rev
1.0

Friday, November 26, 2010

Sheet
1

36

of

36

www.s-manuals.com

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