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Howard Layout PDF
Howard Layout PDF
Howard Layout PDF
Layout Guidelines
Resistor Layout
L L
=
W tW
1
=
qN D
R = Rsh
Resistor Layout
Resistor Layout
Resistor Layout
Typically ,
L >> W
R L W Rsh
W
R
L
W
Rsh
W
Absolute Resistance Error Can Be Minimized by
Maximizing Width W
Layout Guidelines Should Be Observed to Obtain
Good Matching Ratio Between Two Resistors (~
0.1%)
Analog Layout, Howard Luong
Capacitor Layout
MOS Capacitors Using Gate-Oxide Thickness Can Be
Used to Achieve Maximum Capacitance Per Unit Area
Fringing and Parasitic Capacitance Can Be Significant
and Should Be Included for Accuracy
Poly-To-Poly Capacitors Are Good In Terms of
Linearity
Without Poly-To-Poly, Metal-To-Metal Capacitors
Can Be Used
To Minimize Chip Area, Sandwiched-Type Capacitors
Can Be Used
10
Sandwiched-Type Capacitors
C21
11
12
Capacitor Layout
C=
ox
tox
Matched Capacitors
Capacitor Error Proportional To Ratio of The
Perimeter to The Area
A = CoxWL
C L W (W + L) P P
=
+
=
=
2A A
C
L
W
WL
P = Perimeter
A = Area
= W = L
Analog Layout, Howard Luong
K=
C2 A2 x2 y2
=
= 2
C1 A1
x1
K=
A2 P2 x2 + y2
= =
2 x1
A1 P1
14
15
1
)
K
x1
1 1
1
K
Analog Layout, Howard Luong
16
Transistor Layout
Transistor Layout
17
18
RG
1
= 2
RG kn
Odd Number of Fingers :
Cdb ' Csb ' nodd + 1 1
=
=
Cdb Csb
2nodd
2
Even Number of Fingers :
Cd ,out ' neven + 2 Cd ,in ' 1
;
=
=
Cd ,out
2neven
Cd ,in 2
Analog Layout, Howard Luong
19
20
D1
D2
G1
G2
21
22
D1
A2
A1
V Vsup
A2
D1
V Vsup
VR
VR
VL = L(di/dt)
I/O Pin
Vsup
23
24
p+
Circuit
VDD
GND
p+
n+
n well
p- substrate
Guard rings
top views
VB
signal
VB
p+
Cbypass
cross-section views
VB
VB
VB
shields
25
26
27
28
RS
Bondwire
Bondwire / Cable
Pad
Bias Node
VB
IB
Bias
Device
LS
C1
CB
C2
DUT
Package / PCB
29
31
30
References
D. Johns, and K. Martin, Analog Integrated Circuit
Design, New York, Wiley, 1997
P. Gray, et al, Analysis and Design of Analog Integrated
Circuits, New York, Wiley, 4th ed., 2001.
B. Razavi, Design of Analog CMOS Integrated Circuits,
McGraw Hill, 2001
R. J. Baker, H. W. Li, and D. E. Boyce, CMOS Circuit
Design, Layout, and Simulation, IEEE Press, 1998
M. Ismail and T. Fiez, Analog VLSI Signal and
Information Processing, Mc-Graw-Hill, 1994.
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