Cmos1 Feb June15

An Introduction
to
CMOS VLSI Design

LECTURE 1
Presented By:
Yogindra S. Abhyankar
Associate Director & HoD (RC)
Hardware Technology Development Group, CDAC
2015, Centre for Development of Advanced Computing, Pune
Agenda: Lecture 1
About the CMOS Module
Technology: Micro electronics
The MOS Transistor

The NMOS, PMOS and CMOS
Introduction
Wafer
Die
On-chip
connections
Smallest Interconnect ~
1/2000th of Human hair
Acknowledgment: H Veendrick; TI/Koning & Hartman
Introduction
Complexity
Synchronization
Power
Interconnect
Standard Cell
module
contd..
Introduction
contd..
Intel 4004
Microprocessor
1000 Transistors
1 MHz !
Truly
handcrafted
Design
Introduction
1982
90% of ICs
are CMOS !
2014
Memory, MPU, Signal Processor

Design Abstraction Levels

SYSTEM
MODULE
+
GATE
CIRCUIT
Vin
Vout
G
S
n+
DEVICE
D
n+
Module Objective
Introduction to Design and Simulation of
CMOS Digital Integrated Circuits
Technology and Fabrication : a brief discussion
Emphasis on Design & CAD tools
Circuit Layout with MAGIC layout editor
Circuit Simulation with IRSIM, SPICE
Basic cells
Logic gates
Subsystems
Adders, MUX...
Circuit Level
Reference Books
CMOS VLSI Design: A Circuits and Systems Perspective
Neil Weste, David Harris, Ayan Banerjee
Principles of CMOS VLSI Design
- Neil Weste, Kamran Eshranghian

BASIC VLSI DESIGN systems and circuits
D Pucknell, K Eshranghian
Introduction to nMOS and CMOS VLSI System Design

Amar Mukherjee
VLSI Design Techniques for Analog & Digital Circuits

R Geiger, P Allen, N Strader
Digital Integrated Circuits: A Design Perspective

Jan Rabaey
Agenda: Lecture 1
The MOS Transistor

Conductor, Semiconductor & Insulator

Atomic Structure
Valence electron
Nucleus (protons +
neutron)
Phosphorous atom (15)
2, 8, 5
Number of valence electrons

Distance from the nucleus

Energy Diagram
(Band Diagram)
Conduction
Band
Forbidden
Band
Valence
Band
Energy Bands of
an atom

Conductor
Anything that conducts electricity

Valence
electron
Copper (29)
2, 8, 18, 1
Nucleus (protons +
neutron)


Conductor
Silver (47)
2, 8, 18, 18, 1
Valence
electron
Nucleus (protons +
neutron)


Conductor
Gold (79)
2, 8, 18, 18, 32, 1
Valence
electron
Nucleus (protons +
neutron)


Energy Diagram of a Conductor
(Band Diagram)
Free Electrons
Conduction
Band
Valence
Band
Energy Bands of
an atom
No Forbidden Gap
Overlapping of
Conduction &
Valence band
Electrons
Holes

Insulator
Protects from cold/ heat / current
A material having few free electrons

and a high resistivity
(large attraction between nucleus &
electrons)
Atomic structure of these compound
materials, called Polymers
Conduction
Band
Forbidden
Band
Valence
Band
Example:Synthetic rubber,
plastic, SiO2 etc.
Valence electrons are full
Energy Bands of
an atom
Wide Forbidden Band

Semiconductor
Partly Conductor- Partly Insulator
Example:Silicon (Si), Germanium(Ge)

Atomic number
Silicon atom (14)

2, 8, 4
si
Valence electrons
> Conductor
< Insulator
Pure Silicon
atom

Semiconductor
Germanium atom (32)
2, 8, 18, 4
Valence electrons
> Conductor
< Insulator

Semiconductor Silicon Vs Germanium
Material Constant
Melting point (C)
Breakdown field (V/m)
Max. operating temp(C)
Germanium
937
8
70
Silicon
1415
30
150
Generally ICs use Silicon due to its accepted

Military Specifications!

Energy Diagram of a Semiconductor
(Band Diagram)
Free Electrons
Conduction
Band
Forbidden
Band
Valence
Band
Energy Bands of
an atom
Very Small
Forbidden Gap
Electrons
Holes

Silicon Crystal
Large number
of Silicon atoms
Covalent Bonding
Sharing of Valence
Electrons
Si
Si
Si
Si
Types: Intrinsic=> Pure; Extrinsic => Impure

Pure Silicon Crystal has a Stable configuration
(all bonds satisfied) Not useful as it is
Si

Extrinsic Semiconductor
(impure)
Doping Pure Semiconductor with impurities
Group
III (acceptors)
IV
V (donors)
Boron
Aluminium
Silicon
Germanium
Phosphorous
Arsenic

n-type Semiconductor
Si
Addition of pentavalent
atoms to Silicon
Si
Electrons are the

majority current
carriers
5th As
electron
Si
T = 0 K
r
Si
Si
As
Si
Si
Si
Si
Impurity electrons
Conduction band
Ec
Ec
Si
E
Ed
d
Eg
Eg
Valence Ev
Valence Ev
T > 0 K
band T = 0 K 2015, Centre
band
for Development of Advanced Computing, Pune
Donor
levels
r ~ 70
Ed = 0.05 eV

p-type Semiconductor
Addition of Trivalent
atoms to Silicon
Absence
of one
electron
Si
Si
Al
Si
Si
Holes are the majority

current carriers
Si
+
Si
Ea ~ 0.06 eV
(to pullout e
from Si )
Si
Al
Si
Si

p-n Junction
P-type and n-type
brought together
Hole diffusion
Electron diffusion
(1) Diffusion
(2) Depletion
(3) Drift
Hole drift
Electron drift
Classification of IC Technology
Based on Number of Devices used (FET)
Based on Feature size of the process
Based on Number of Devices used (FET)
Type Devices
SSI
MSI
LSI
VLSI
VVLSI
Year Function
1-100
1960
100-1000
1965
1000-10000 1970
10000-100000 1975
100,000 +
Gates, Op-amp, Linear

Registers, Filters
Microprocessors, A/D
Memory,Computers,DSP
System on a chip
Based on the Feature size of the process

Feature Size: Manufacturing capability
Metal
How small ?
Oxide
Semiconductor
Source
Gate
Drain
First IC
25
W
n
p substrate
Feature Size 1970

Earlier in Terms of Gate
Length L
1970-80
1980-90
19902006-09
2011
7-10
5
< 2
0.75 0.25 0.18...
65 nm, 45 nm, 32 nm
22 nm
Deep
Sub-micron
processes
Acknowledgment: Intel,
2013: 14nm Fab
ITRS
Design Challenges: Deep Sub-Micron Digital Circuit Design

Microscopic issues
Ultra-high speeds
Power dissipation and supply
rail drop (IR)
Growing importance of
interconnect
Noise, crosstalk
Reliability, manufacturability
Electromigration (EM)
Clock distribution
Global clock challenging
Macroscopic issues
Time-to-market
Design complexity
(millions of gates)
High levels of
abstractions
Reuse and IP,
portability
Systems on a chip
(SoC)
Tool interoperability
Wafer
Single die
How many Devices can be fabricated on a

given piece of Silicon ?
Wafer
Size: 4 inch Silicon Wafer Technology: 5

Transistor
2
N5 = r

= in)2 ~ x Transistors

A 1/10 decrease in feature size => Increase in device count by ~ 100 times
Advantages of reducing the Feature Size
Cost Reduction
Possibility of more complex designs
Increase in speed (linearly)
Micro Electronics
Micro Electronics
Inert Substrate
Processes (Good Resistors)
Active Substrate
Silicon
GaAs
Thick film Thin film
MOS
Current flow: majority

none through gate
Bipolar
CMOS
TTL
BiCMOS
ECL
majority+minority
through base
pMOS, nMOS, CMOS

pmos: (1960s) calculators
poor mobility than nmos
nmos: (1970s) p 4004, 8080 for speed

Excellent density, Performance, Proven, consumes power when idle
cmos: (1980s) p + n
Additional flexibility
Low power consumption
Operate between 2V and 12V
Excellent noise immunity (40%)
Portability
Design simplicity
More processing steps
Rise & fall time of the same order
Bipolar, CMOS, BiCMOS

Bipolar: High gain factor, lower noise
More Suitable for Analog applications
CMOS: Low power, reasonable performance,

high packing density
More attractive for digital controls, storage &
signal processing
BiCMOS: High speed, Suitable for mixed

analog/ Digital applications;
Digital I/O circuits, SRAM control
Cost 30% extra to CMOS

Agenda: Lecture 1
The MOS Transistor

MOSFET
(Metal Oxide Semiconductor Field Effect Transistor)
A MOSFET or MOS transistor, is a device where current
through a channel between the source and drain is controlled
by the voltage applied to the gate. Metal
Oxide
Semiconductor
Source
Gate
Drain
W
n
Body
p substrate
nMOS : majority current carriers are electrons

pMOS : majority current carriers are holes.
The MOS Transistor

Polysilicon
Aluminum
Transistor gate, source, drain all have capacitance

I = C (dV/dt)
-> dt = (C/I) dV
Capacitance and current determine speed
Cross-Section of CMOS Technology
MOS system under external bias

Gate and body form MOS capacitor
Operating modes
Accumulation
Depletion
Inversion
Vg < 0
+
-
polysilicon gate
silicon dioxide insulator
p-type body
(a)
0 < Vg < Vt
+
-
depletion region
(b)
Vg > V t
+
-
(c)
inversion region
depletion region
MOS transistor Types and Symbols

D
NMOS
Enhancement
D
PMOS S
Enhancement
NMOS
Depletion
PMOS
Depletion
4th terminal, body, not shown; connected to dc supply of same type MOS
MOS Transistor Types

Enhance mode MOS: No conducting
channel region at zero gate bias (formation of
the channel is enhanced by gate voltage);
Depletion mode MOS: Conducting channel

already exists at zero gate bias; (During
fabrication, a thin channel is built under the gate);
MOS Operation:Terminal Voltages

Mode of operation depends on Vg, Vd, Vs
Vgs = Vg Vs
Vgd = Vg Vd
Vds = Vd Vs = Vgs - Vgd
Vg
Vs
Source and drain are symmetric diffusion

terminals
nMOS body is grounded.
+
Vgd
-
+
Vgs
-
Vds
Vd
MOS Operation
Three Regions:
1 > Cut-off: No current flows (except
the source-drain leakage current).
2 > Linear: Weak inversion; Drain current
increases linearly with gate voltage, drain voltage
3 > Saturation: Strong inversion; Drain current
independent of drain voltage.
nMOS with no gate voltage

VGS = 0
Small depletion
layer
Gate (conductor )
G
S
Sio2 insulator
D
Cutoff
If VGS = 0;
n-Source, isolated from n-Drain, through p-Substrate
Back-to-back diodes formed
No current between the Source & Drain (IDS = 0)
nMOS Operation: 0 < VGS < VT
Depletion region
VDS = 0
G
S
Cutoff
IDS = 0
Application of a small positive voltage at gate starts formation of a

depletion layer under the gate in the p-substrate: holes repelled
At VGS = Vt , surface completely depleted of charge
Insulator Sio2 Prevents current loss
nMOS Operation: Inversion Layer

Vds = Vgs - Vgd
G
VGS > VT
VDS = 0
D
S
n+
n n n n n n
n+
Vgd = Vgs
Inversion layer
If the gate voltage is further increased, (VGS Vt ), the p-region
under the gate changes to n region, providing a conduction path
between the source and drain. This new inverted layer (from p to n) is
called the inversion layer or the inverted channel.
nMOS Operation: Linear

VGS > VT
VDS small + ve
0<
G
VDS < VGS - VT
IDS = f (VGS, VDS)

S
n+
D
n n n
nn n n
n+
ID > 0
Extra Depletion
For VDS > 0, IDS starts flowing
I D VDS
Device acts as Voltage controlled Resistor
Increasing VDS causes extra depletion near drain (due to the pd across the
region by the current flow), decreasing channel depth
nMOS Operation: Saturation (pinch-off)

VGS > VT
G
IDS ~ f (Vg)
n+
nn
VDS = VGS VT
(pinch-off)
VDS > VGS - VT
n+
For VDS = VGS VT, channel pinches-off;

Current remains constant or saturates no longer a function of VDS
IDS ~ f (Vg) ; The current flow is due to drift
Electron from S channel , injected into depleted part of channel
accelerated toward Drain by high field induced by VDS
Current-Voltage Relations
Cut-off Region:
VGS < VT
IDS = 0
p ~ (1/2 or 1/3) n
[Pinch-off occurs when VDS = VGS-VT]
Current Determinates
For a fixed VDS and VGS (> VT), IDS is a function
of
- the distance between the source and drain L
the channel width W
the threshold voltage VT
the thickness of the SiO2 tox
the dielectric of the gate insulator (SiO2) ox
the carrier mobility
for nfets: n = 500 cm2/V-sec
for pfets: p = 180 cm2/V-sec
MOS transistor: Types and Symbols

D
G
S
S
NMOS
Enhancement
NMOS
Depletion
PMOS
Enhancement
PMOS Depletion
I-V Characteristics: Ids ?
In Linear region, Ids depends on
How much charge is in the channel?

How fast is the charge moving?
I ds
Qchannel
Qchannel
Contd
MOS structure looks like parallel plate

capacitor while operating in inversion
Gate oxide channel
Qchannel = CV
C = Cg = oxWL/tox = CoxWL
V = Vgc Vt = (Vgs Vds/2) Vt
Cox = ox / tox
gate
Vg
polysilicon
gate
W
tox
n+
n+
SiO2 gate oxide

(good insulator, ox = 3.9)
+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+
n+
n+
Vds
p-type body
p-type body
Carrier velocity & Time t
contd..
Charge is carried by e Carrier velocity v proportional to lateral E-field

between source and drain
v = E
called mobility ----(1)
E = Vds/L
---- (2)
Time for carrier to cross channel:
t=L/v
nMOS Linear I-V:
Ids
Now we know
How much charge Qchannel is in the channel
How much time t each carrier takes to cross
Qchannel
I ds
t
W
Cox
L
V V Vds
gs t
2
V
Vgs Vt ds Vds
2
V
ds
W
= Cox
L
nMOS Saturation I-V Ids

If Vgd < Vt, channel pinches off near drain
When Vds > Vdsat = Vgs Vt
Now drain voltage no longer increases current

V
I ds Vgs Vt dsat
2
gs
Vt
V
dsat
nMOS I-V Summary

Shockley 1st order transistor models

Vds
I ds Vgs Vt
2
Vgs Vt
Vgs Vt
V V V
ds
ds
dsat
Vds Vdsat
W
= Cox
L
cutoff
linear
saturation
Example
For a 0.6 m process from AMI Semiconductor
tox = 100
= 350 cm2/V*s
Vt = 0.7 V
Vgs = 0, 1, 2, 3, 4, 5
Use W/L = 4/2 l
Vgs = 5
2
Ids (mA)
Plot Ids vs. Vds
2.5
1.5
Vgs = 4
1
Vgs = 3
0.5
0
Vgs = 2
Vgs = 1
3.9 8.85 1014 W

W
W
Cox
350
120
A /V 2

8
L
100 10
L
3
Vds
pMOS I-V
All dopings and voltages are inverted for pMOS
Source is the more positive terminal
Mobility p is determined by holes
Typically 2-3x lower than that of electrons n

120 cm2/Vs in AMI 0.6 m process
Thus pMOS must be wider to

provide same current
Vgs = -1
Vgs = -2
-0.2
Vgs = -3
Ids (mA)
In this class, assume

n / p = 2
-0.4
Vgs = -4
-0.6
-0.8
-5
Vgs = -5
-4
-3
-2
Vds
-1
The Threshold Voltage

It is the voltage (VT) applied between
the gate and source of an MOS device
below which the drain-to-source
current Ids drops to zero (channel is
cut-off).
VT is a function of a number of parameters
including the following:
1. Gate material
2. Gate insulation material
3. Gate insulator thickness
4. Channel doping
5. Voltage between source and
substrate Vsb
6. Temperature (inversely
proportion)
When
VSB=0
The Threshold Voltage

VT changes with VSB ; although by a small amount
Not so common way to control the drain-to-source
current Ids
....
Summary
MOSFET most widely used device & Fundamental
building block of ICs Digital, Analog, memory
Small size => Dense circuits
Low power, High Speed => chips for GHz processors
Transistor states: ON, OFF

Regions of Operations: Cutoff, Linear, Saturation
Threshold Voltage
Faster Transistors
Transistor Frequency (vs processor frequency)
Importance of Transistor current Ids
Mobility
Transistors in Modern ICs
Conclusion
Continuing Research in Device Technology is fulfilling the
future needs of Industry
Full custom layout designs are used where Density and
Performance are critical :
Standard Cell library, Memory, Portions of microprocessors
Most of the ICs use Enhanced mode transistors;

Depletion mode transistors mostly in analog ICs.

Cmos1 Feb June15

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An Introduction

CMOS VLSI Design

The MOS Transistor

2015, Centre for Development of Advanced Computing, Pune

2015, Centre for Development of Advanced Computing, Pune

2015, Centre for Development of Advanced Computing, Pune

Memory, MPU, Signal Processor

Design Abstraction Levels

2015, Centre for Development of Advanced Computing, Pune

Principles of CMOS VLSI Design

- Neil Weste, Kamran Eshranghian

Introduction to nMOS and CMOS VLSI System Design

VLSI Design Techniques for Analog & Digital Circuits

Digital Integrated Circuits: A Design Perspective

The MOS Transistor

2015, Centre for Development of Advanced Computing, Pune

Conductor, Semiconductor & Insulator

Number of valence electrons

Conductor, Semiconductor & Insulator

Conductor, Semiconductor & Insulator

Anything that conducts electricity

Number of valence electrons

Conductor, Semiconductor & Insulator

Number of valence electrons

Conductor, Semiconductor & Insulator

Number of valence electrons

2015, Centre for Development of Advanced Computing, Pune

Conductor, Semiconductor & Insulator

2015, Centre for Development of Advanced Computing, Pune

Conductor, Semiconductor & Insulator

Protects from cold/ heat / current

A material having few free electrons

Valence electrons are full

Wide Forbidden Band

2015, Centre for Development of Advanced Computing, Pune

Conductor, Semiconductor & Insulator

Partly Conductor- Partly Insulator

Example:Silicon (Si), Germanium(Ge)

Silicon atom (14)

2015, Centre for Development of Advanced Computing, Pune

Conductor, Semiconductor & Insulator

Conductor, Semiconductor & Insulator

Generally ICs use Silicon due to its accepted

Conductor, Semiconductor & Insulator

2015, Centre for Development of Advanced Computing, Pune

Conductor, Semiconductor & Insulator

Types: Intrinsic=> Pure; Extrinsic => Impure

Conductor, Semiconductor & Insulator

Doping Pure Semiconductor with impurities

2015, Centre for Development of Advanced Computing, Pune

Conductor, Semiconductor & Insulator

Electrons are the

Conductor, Semiconductor & Insulator

Holes are the majority

2015, Centre for Development of Advanced Computing, Pune

Conductor, Semiconductor & Insulator

2015, Centre for Development of Advanced Computing, Pune

Gates, Op-amp, Linear

2015, Centre for Development of Advanced Computing, Pune

Based on the Feature size of the process

Feature Size 1970

2015, Centre for Development of Advanced Computing, Pune

2013: 14nm Fab

Design Challenges: Deep Sub-Micron Digital Circuit Design