EE 215C

Win. 13

B. Razavi
HO #11

Homework #3
Due Tue., Feb. 5, 2013
In this homework, we study the front end of a simple heterodyne receiver. Part of the circuit is similar to the
cascade studied in previous homeworks. All transistors have a channel length of 0.18 m. For the LO, assume
a frequency of 5.13 GHz, a common-mode level of 1.7 V, and a peak-to-peak differential amplitude of 0.9 V.
The inductor must be modeled as shown, where RP is chosen to give a Q of 4 at the frequency of interest and
CP = 5 fF for every nanohenry of inductance.
VDD = 1.8 V

60
0.18

0.1 p

VIF

M1
50

900

0.1 p

6 nH
0.5 p

M4

M3

VLO

M2

V in

Ideal

VDD

3 mA
0.15 mA

Inductor Model

CP

0.2 W2

0.18

RP

10k

0.25 pF

CP

(a) Determine the width of M2 to obtain resonance at 5.2 GHz.

(b) Determine the width of M3 and M4 to achieve maximum conversion gain, defined as the magnitude of the
IF component divided by Vin =2. What is the voltage conversion gain of the mixer under this condition?
(c) Determine the LO leakage to the antenna and show the leakage path.
(d) Compute the output dc offset if M3 and M4 suffer from a threshold mismatch of 15 mV and the LO contains
a 6% second harmonic.
(e) Calculate the IP3 of the first stage and the overall circuit. Which stage would you consider as the IP3
bottleneck?