EXPERIMENT-1

Aim: PLOT INPUT AND OUTPUT CHARACTERISTIC OF NMOS AND

PMOS FOR DIFFERENT TECHNOLOGY NODE.
1. FOR THRESHOLD VOLTAGE:

(i)For NMOS

(a) AT Vds = 0.1

SCHEMATIC DIAGRAM:

NETLIST:
* C:\Users\girishkumar\DIC Lab\EXP 1\Ro\NMOS\Vgs1\Draft1.asc M1
N002 N001 0 0 NMOS l=180n w=1u
Vgs N001 0
Vds N002 0 0.1
.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~2\LTC\LTSPIC~1\lib\cmp\standard.mos
.dc Vgs 0.0 1.8 0.01
.inc "C:\Users\Girishkumar\Desktop\180nm_bulk.txt"
.backanno
.end

GRAPH:

RESULT:
Vth= 0.457V

(b) At Vds= 1.8 V

SCHEMATIC DIAGRAM:

NETLIST:
* C:\Users\Rishabh\Desktop\DIC Lab\EXP 1\Ro\NMOS\Vgs1\Draft1.asc
M1 N002 N001 0 0 NMOS l=180n w=1u
Vgs N001 0
Vds N002 0 1.8
.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~2\LTC\LTSPIC~1\lib\cmp\standard.mos
.dc Vgs 0.0 1.8 0.01
.inc "C:\Users\Rishabh\Desktop\180nm_bulk.txt"
.backanno
.end

GRAPH:

RESULT:
Vth = 0.455V

(ii)FOR PMOS
(a) VDS = -0.1
SCHEMATIC DIAGRAM:

NETLIST:
* C:\Users\girish\Desktop\DIC Lab\EXP 1\Ro\PMOS\VGS=-0.1\Draft2.asc M1
N002 N001 0 N003 PMOS l=180n w=1u
Vgs N001 0 Vds
N002 0 -0.1
.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~2\LTC\LTSPIC~1\lib\cmp\standard.mos
.dc Vgs -1.8 0.0 0.01
.inc "C:\Users\Girish\Desktop\180nm_bulk.txt"
.backanno
.end

GRAPH:

RESULT:
Vth= -0.49V

(b)VDS= -1.8

SCHEMATIC DIAGRAM:

NETLIST:
* C:\Users\girish\Desktop\DIC Lab\EXP 1\Ro\PMOS\VGS=-0.1\Draft2.asc M1
N002 N001 0 N003 PMOS l=180n w=1u
Vgs N001 0 Vds
N002 0 -1.8
.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~2\LTC\LTSPIC~1\lib\cmp\standard.mos
.dc Vgs -1.8 0.0 0.01
.inc "C:\Users\girish\Desktop\180nm_bulk.txt"
.backanno
.end

GRAPH:

RESULT:
VTH = -0.65V

2. FOR OUTPUT RESISTANCE:

(i) FOR NMOS
(a) VGS = 0.1V
SCHEMATIC DIAGRAM:

NETLIST:
* C:\Users\girish\Desktop\DIC Lab\EXP 1\Ro\NMOS\Vgs1\Draft1.asc M1
N002 N001 0 0 NMOS l=180n w=1u
Vgs N001 0 0.1
Vds N002 0
.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~2\LTC\LTSPIC~1\lib\cmp\standard.mos
.dc Vds 0.0 1.8 0.01
.inc "C:\Users\girish\Desktop\180nm_bulk.txt"
.backanno
.end

GRAPH:

RESULT:
RO cannot find out as device is in cutoff region.

(b) VGS = 1.8V

SCHEMATIC DIAGRAM:

NETLIST:
* C:\Users\girish\Desktop\DIC Lab\EXP 1\Ro\NMOS\Vgs1\Draft1.asc M1
N002 N001 0 0 NMOS l=180n w=1u
Vgs N001 0 1.8
Vds N002 0
.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~2\LTC\LTSPIC~1\lib\cmp\standard.mos
.dc Vds 0.0 1.8 0.01
.inc "C:\Users\girish\Desktop\180nm_bulk.txt"
.backanno
.end

GRAPH:

RESULT:
Ro =16.1K

(ii)FOR PMOS
(a)Vgs = -0.1

SCHEMATIC DIAGRAM:

NETLIST:
* C:\Users\girish\Desktop\DIC Lab\EXP 1\Ro\PMOS\VGS=-0.1\Draft2.asc M1
N002 N001 0 0 PMOS l=180n w=1u
Vgs N001 0 -1.0
Vds N002 0 -0.1
.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~2\LTC\LTSPIC~1\lib\cmp\standard.mos
.dc Vgs -1.8 0.0 0.01
.inc "C:\Users\girish\Desktop\180nm_bulk.txt"
.backanno
.end

GRAPH:

RESULT:
Ro cannot be find out as device is in cut off region.

(b)Vgs = -1.8

SCHEMATIC DIAGRAM:

NETLIST:
* C:\Users\girish\Desktop\DIC Lab\EXP 1\Ro\PMOS\VGS=-0.1\Draft2.asc M1
N002 N001 0 N003 PMOS l=180n w=1u
Vgs N001 0 -1.8
Vds N002 0
.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~2\LTC\LTSPIC~1\lib\cmp\standard.mos
.dc Vds -1.8 0.0 0.01
.inc "C:\Users\girish\Desktop\180nm_bulk.txt"
.backanno
.end

GRAPH:

RESULT:
Ro =20K

3. Calculation of sub threshold:

(i) FOR NMOS
For Vds=1.8V
SCHEMATIC DIAGRAM:

NETLIST:
* C:\Users\girish\Desktop\DIC Lab\EXP 1\Vth\NMOS\Vds=1.8\Draft1.asc M1
N002 N001 0 N003 NMOS l=180n w=1u
Vgs N001 0
Vds N002 0 1.8
.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~2\LTC\LTSPIC~1\lib\cmp\standard.mos
.dc Vgs 0 1.8 0.01
.inc "C:\Users\girish\Desktop\180nm_bulk.txt"
.backanno
.end
.end

GRAPH:

ResultSub threshold=53.5mv/decade

(ii)For PMOS
(a)Vds=
-1.8v

SCHEMATIC DIAGRAM:

NETLIST:
* C:\Users\girish\Desktop\DIC Lab\EXP 1\Vth\PMOS\1.8\Draft1.asc Vgs
N001 0
Vds N002 0 -1.8
M1 N002 N001 0 N003 PMOS
.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~2\LTC\LTSPIC~1\lib\cmp\standard.mos
.dc Vgs 0.0 -1.8 -0.01
.inc "C:\Users\girish\Desktop\180nm_bulk.txt"
.backanno
.end

GRAPH:

Result : Subthresold = 54.44 mv/decade

4. Drain Induced Barrier Lowering

DIBLnmos=Vth/Vds=0.001
DIBLpmos=Vth/Vds=0.094

GIRISH KUMAR

BT14ECE032