Custom IC Design Lab (Fall 2011-12)

Experiment Date: 18th September 2011

Submitted Date: 2th November 2011
Name: LITHIN BALU (11MVD0013)

8. Post layout delay calculation using RCX

OBJECTIVE:
To perform the RCX check and calculate the post layout propagation delay of the
CMOS Inverter
CMOS NAND gate.
Complex combinational circuit (A(B+C)+D)

CIRCUIT DIAGRAM:
Circuit Diagram and layout of CMOS Inverter Gate:

Circuit Diagram and layout of NAND Gate:

Methods:

Custom IC Design Lab (Fall 2011-12)

Draw the schematic diagram of the CMOS NAND gate as shown in the above
circuit. Assigned input Pins (A, B, Vdd, Vss) and output pin (Vout).
After checking and saving the circuit, layout is plotted using layout XL tool.
Run the RCX check and av extracted view is obtained.
Post layout propagation delay is calculated for NAND gate and compared with
propagation delay calculated circuit stimulation.
Circuit Diagram and layout of Combinational circuit (A(B+C)+D):

Methods:
Draw the schematic diagram of the Combinational circuit (A(B+C)+D) as
shown in the above circuit. Assigned input Pins (A, B,C,D, Vdd, Vss) and
output pin (Y).
After checking and saving the circuit, layout is plotted using layout XL tool.
Run the RCX check and av extracted view is obtained.
Post layout propagation delay is calculated for Combinational circuit
(A(B+C)+D)

stimulation.

and compared with propagation delay calculated circuit

Custom IC Design Lab (Fall 2011-12)

OBSERVATIONS:
1. RCX Result for CMOS inverter Gate:

Post layout simulation:

Custom IC Design Lab (Fall 2011-12)

2. RCX Result for NAND Gate:

Post layout simulation:

3. RCX Result for Complex combinational circuit (A(B+C)+D):

Custom IC Design Lab (Fall 2011-12)

Post layout simulation:

Table:1

Custom IC Design Lab (Fall 2011-12)

Pre-layout

Post layout

simulation
tPHL(ps)

tPLH(ps)

simulation
tPHL(ps)

tPLH(ps)

35.36

138.4

41.1

145.2

3.683

145.1

16.91

159.7

Worst Case*

375.2

199.1

446.6

277.7

Best Case**

162.3

188.6

280.1

294.3

CMOS
INVERTER
NAND GATE
(A(B+C)+D)

*Worst Case Input Combination:

A = 1; B=0; C=0-1; D=0;

**Best Case Input Combination:

A = 1-0; B=1-0; C=0; D=0;

RESULTS:
RCX run is performed and the post layout delay is calculated for the following
circuits:
CMOS Inverter
CMOS NAND gate.
Complex combinational circuit (A(B+C)+D)
It is observed that propagation delay is increased slightly due to presence of the
resistance and capacitance in layout layer

REFERENCES
Digital Integrated Circuits by M. Rabaey