VLSI Design

Adders

Awais M. Kamboh

Slide 1

Addition
Speed of the adder has a big impact on the clock speed of the processor, rather it
determines the clock speed of the processor.

How to Add
How to add two numbers, e.g. 747 + 854
Digit by digit: Start from LSB side, add two digits, add carry to next digit.

Sequential Effect
The challenge is that we cannot do the last addition till we know the carry that comes from
the digits before it. So there is a sequential effect.
We cannot compute sum from all the bits simultaneously because we do not know the
answer of previous digits.

Binary Addition
Circuits use binary representation.
Awais M. Kamboh

Slide 2

Full Adder
A
Cin
Cin

B
Full
adder
Full

adder

Cout
Cout

Sum

Sum

S == AA
B
S
B Ci C i
= ABC i + ABC i + ABCi + ABCi

= ABC i + ABC i + ABCi + ABCi

C o = AB + BCi + ACi

C o = AB + BCi + ACi
Awais M. Kamboh

Slide 3

Sum and Carry

Define 3 new variable which ONLY depend on A, B

Generate (G) = AB (Both A & B are 1)

Propagate (P) = A B (Either A or B is 1)
Delete (Kill) =A B (Both A & B are 0)

Similarly, we can also derive expressions for S and Co based on K and P

Awais M. Kamboh

Slide 4

Simplest Adder: Ripple Carry

Awais M. Kamboh

Slide 5

Negative Numbers
Sign-Magnitude Representation
Not very handy in terms of arithmetic
0|01011 = +11
1|01011 = -11

2s Complement Representation
Invert all bits, then add 1
01011 -> 10101 = -11
(MSB=1 if number is negative)
Inverse of 2s Complement is the same, invert all bits then add 1
Good things about 2s complement is that we do not need to worry about sign
of the numbers, e.g. add +11 with -11 should give 0.
We throw away the final carry

Awais M. Kamboh

Slide 6

Direct Implementation: Full Adder

VDD
VDD
A

Ci

B
A

B
B

Ci
A

Ci

VDD

Ci

A
Ci

VDD
A
Co

Ci

28 Transistors
Awais M. Kamboh

Slide 7

CMOS Full Adder

28 Transistors
Awais M. Kamboh

Slide 8

Inversion Property
A

Ci

A
A

FA

Co

C iCi

B
B

FA
FA

CCoo

Ci

SS
S A B C i = S A B Ci

S A B C i = S A B C

C o A B C i = Co A B Ci C A B C = C A B
o
i
o

Awais M. Kamboh

Slide 9

Modified FA - Minimize Critical Path

Even cell
A0

B0

Ci,0

A1

B1

Co,0

A2

Odd cell

B2

Co,1

A3

B3

Co,2

Co,3

FA

FA

FA

FA

S0

S1

S2

S3

Exploit Inversion Property,

Remove the inverter for Co from each stage
Reduce Inverting Stages
Awais M. Kamboh

Slide 10

Mirror Adder

Awais M. Kamboh

Slide 11

Sizing the Mirror Adder

Awais M. Kamboh

Slide 12

Sizing the Mirror Adder

Awais M. Kamboh

Slide 13

Mirror Adder Stick Diagram

VDD

Ci

A Ci

Co

Ci

Co
S
GND

Awais M. Kamboh

Slide 14

Mirror Adder - Summary

The NMOS and PMOS chains are completely symmetrical.

A maximum of two series transistors can be observed in the
carry-generation circuitry.

When laying out the cell, the most critical issue is the
minimization of the capacitance at node Co.

The capacitance at node Co is composed of four diffusion

capacitances, two internal gate capacitances, and six gate
capacitances in the connecting adder cell .

The transistors connected to Ci are placed closest to the output.

Only the transistors in the carry Propagate stage have to be

optimized for optimal speed. All transistors in the sum stage can
be minimal size.

Awais M. Kamboh

Slide 15

Carry Bypass Adder

Awais M. Kamboh

Slide 16

Carry Bypass Adder

Awais M. Kamboh

Slide 17

Carry Ripple vs Carry Bypass

Awais M. Kamboh

Slide 18