CMOS, Mixed Signal and Radio Frequency VLSI Design, NMEICT, T210KT-2017

Analog Design: Full Marks-200

Q1. For all circuits in Fig. Q1, assume all transistors to be in saturation.
(a) For the single stage amplifiers given in fig. Q1(a) to (c), find the expression for low frequency small
signal gain (Vout/Vin) using small signal analysis.
[3x5]

(a)

(b)

(c)

Q2.

Fig. Q2

In fig. Q2 , RG1||RG2 = 50K, Rs = 10K, CL = 1pF, Iref = 0.1mA. VA1 = VA2 =50V. VDD = 2V. ,
(W/L)1 = 40 , (W/L)2 =20, (W/L)3-6 = 30, L1-6 = 1m , Vtn = |Vtp| = 0.4V .
For M1-6, Cgs = 0.003xW pF and Cgd = 0.001xW pF, Cdb ~0, Csb ~0 (where W is the transistor width in
m), find :
(i)
(ii)
(iii)
(iv)
(v)

Minimum value of Vb applicable for saturation region operation of the amplifier.

Small signal voltage gain from Vin to Vx.
Small signal voltage gain from Vin to Vout.
High frequency poles at Vo, VG1, VD1.
Maximum allowed output voltage swing and hence the allowed input voltage swing for the
case when Vb = 1 V
[5x5]

Q4. For the differential amplifier in fig. Q4, Kn = Kp = 0.1mA/V2 where Kn,p = n,pCox(W/L).
n= | np| = 0.02 V-1. Vtn= |Vtp| = 0.4V. IS = 0.2mA. VDD = 3V, VSS= 0V. Assume that the devices in the
two branches are well matched.
(i)
(ii)
(iii)

Find the input common mode range. [7.5]

Find the maximum allowed output voltage swing for an applied differential input with
common mode voltage = 1V. [7.5]
For common mode voltage 1V, find the small signal differential input to single ended
output voltage gain and the maximum allowed input voltage swing. [10]

Fig. 4

Fig. Q8
Q.8
(a) For the differential pair shown in fig. 7, find the expression for input referred noise-voltage in terms
of small signal device parameters. Based on the noise expression, determine the sizing strategy for
minimizing the input referred noise of the circuit. Find the expression for 1/f noise corner frequency.
[12.5]
(b) How does the expression for input referred noise change for (i) diode connected load and (ii) currentsource load (fully differential).
[12.5]