The document proposes a hybrid cache architecture using low-power STT-RAM and SRAM. It develops a controlled cache block that dynamically varies the memory control during runtime to drastically reduce wasted power from unnecessary wait statements. The dynamic adaptive control block monitors SRAM operations to recycle wasted energy, reduce data wait time, and enable variable memory control options during runtime. The proposed system provides advantages of dynamic adaptive control, power recycling, and reduced data wait time.
The document proposes a hybrid cache architecture using low-power STT-RAM and SRAM. It develops a controlled cache block that dynamically varies the memory control during runtime to drastically reduce wasted power from unnecessary wait statements. The dynamic adaptive control block monitors SRAM operations to recycle wasted energy, reduce data wait time, and enable variable memory control options during runtime. The proposed system provides advantages of dynamic adaptive control, power recycling, and reduced data wait time.
The document proposes a hybrid cache architecture using low-power STT-RAM and SRAM. It develops a controlled cache block that dynamically varies the memory control during runtime to drastically reduce wasted power from unnecessary wait statements. The dynamic adaptive control block monitors SRAM operations to recycle wasted energy, reduce data wait time, and enable variable memory control options during runtime. The proposed system provides advantages of dynamic adaptive control, power recycling, and reduced data wait time.
In the proposed design dynamic and adaptive STT-RAM and SRAM partitions are designed. We develop a controlled cache block which dynamically varies the memory control during run time itself. This modeling is established to drastically reduce the power which is wasted through unwanted wait statements executed during the operation.Dynamic adaptive control block keep on monitors the SRAM Operation to recycle the energy wasted as well as reduce the data wait time and enables variable options for memory controls during Run time. Advantages of Proposed System