Interview Questions

28/03/2017 WhatkindofinterviewquestionswilltheyasktoaFPGAengineer?
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Balamurugan Jeyachandran, FPGA design Engineer interviews?
UpdatedJan25
Whatkindsofquestionsareaskedinadataengineer
While there are plenty of questions that can be targeted for the candidates however interviewatFacebook?
we cannot describe all here. I'm listing most frequent ones
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Okay, so as request by few, I shall provide some simple answers here-in
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1. What is speed grade and how do you select FPGA as per requirements
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a. Speed Grade is what that determines how max a clock can run in FPGA.
Companies use dierent values, while -1, -2 indicates the scale. Higher the 5,775Views
grade, higher the cost of FPGA LastAskedSep23,2016
Edits
2. What is the maximum possible speed achievable for a given device say
Virtex6 device (some speed grade)
a. The Fmax is determined by Flop-to-Flop timing using shortest route (CLB)

with least clock skew. To put it simple, usually this is calculated based on
logic levels between a source to destination path
3. What is logic level
a. Number of logics levels in your combo circuit. Google for more info
4. How do you code to reduce power in FPGA design
a. Avoid reset for FPGA
b. Clock Gate
c. Use
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28/03/2017 WhatkindofinterviewquestionswilltheyasktoaFPGAengineer?Quora
d. Avoid overconstraining 1 1
e. Reduce Device temperature (cooling solution)
f. Use clk_en and control enable for all Memory
g. Use LUT for smaller memory. BRAM takes more power
5. What is clock gating and how do you do it in FPGA
a. Xilinx and Altera provides primitive components for this. Check them
6. How do you manage multiple clocks and how do you route them
a. CDC tools can help this like Spyglass, etc. But asynchronous transfers
must be handles carefully in design and later they can be assigned false
path for the tool to go easy on compilation
7. How do you do IO planning and can you explain few types of IO types
8. how do add debug probes for chipscope and what are the benets inserting it
and inferring it?
a. Inferring it along with your RTL gives you freedom of debugging

whenever required. Adding it as a probe requires you to sort the netlist le
and break up your head in nding the net names.
b. Sometimes some logic needs to be always put on JTAG for status/debug.
9. How do you program multiple FPGA images in ash and load?
a. Check google on this
10. How do you control reset logic
a. For FPGA, global reset is sucient. Use async reset for internal logic and
sync that reset in main clk (if they are in same clock, else use accordingly)
b. Always assert the reset asynchronously and de-assert synchronously with

clock
11. How do you do STA
12. What are the timing constraints that you do for a typical design having
synchronous and asynchronous logic.
a. For async, false path or TIG constraints. We do not do any constraint for
async path if it is taken care in RTL
13. How does the RTL logic convert to logic gate, say a comparator or counter,
please describe
14. Can you write a code in RTL for a debounce logic or 9-bit counter?
15. Some questions about RTL coding for FPGA primitive components, what are
the primitive components and what have you used.
a. BUFGMUX, ibu, obu, etc
Hope you get to know about this. This is just some set of questions.
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Evgeni Stavinov, works at Xilinx

WrittenJan19,2016
I usually ask the following questions:
- Warm-up questions. For example: convert 14 into hex, binary, and octal (about third
of candidates cannot do that)
- Understanding of digital logic: setup and hold, pipelines, latency and throughput,
etc.
- FPGA architecture questions: how dierent circuits are synthesized, process of

timing closure, dierences between FPGA and ASICs, clock and reset schemes
- Good knowledge of hardware description language (SystemVerilog)
2.6kViewsViewUpvotes
Upvote 8 Downvote Comment
Adi, Engineer
WrittenJan13
refer to this for general guidelines.
How can I be a guru at FPGA & VLSI design and verication?

401ViewsViewUpvotesAnswerrequestedbyRameshMogili
Upvote 1 Downvote Comment
Fred Diggs, Digital logic designer

WrittenJan27,2016
A question about clock domain crossing is typical in an FPGA interview. For example,
a signal derived in clock domain A is used in a sequential process in clock domain B.
What can potentially happen if you use the signal directly in clock domain B? What is
the proper way to handle the signal before using it in clock domain B?
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28/03/2017 WhatkindofinterviewquestionswilltheyasktoaFPGAengineer?

Answer Request Follow 17 Comment Share Downvote UpdateYourInterests

grade, higher the cost of FPGA LastAskedSep23,2016

a. The Fmax is determined by Flop-to-Flop timing using shortest route (CLB)

3. What is logic level

4. How do you code to reduce power in FPGA design

a. Avoid reset for FPGA

f. Use clk_en and control enable for all Memory

g. Use LUT for smaller memory. BRAM takes more power

5. What is clock gating and how do you do it in FPGA

a. Inferring it along with your RTL gives you freedom of debugging

b. Sometimes some logic needs to be always put on JTAG for status/debug.

9. How do you program multiple FPGA images in ash and load?

a. Check google on this

10. How do you control reset logic

b. Always assert the reset asynchronously and de-assert synchronously with

11. How do you do STA

a. BUFGMUX, ibu, obu, etc

Upvote 10 Downvote Comments 3+

Evgeni Stavinov, works at Xilinx

I usually ask the following questions:

- FPGA architecture questions: how dierent circuits are synthesized, process of

- Good knowledge of hardware description language (SystemVerilog)

Upvote 8 Downvote Comment

refer to this for general guidelines.

How can I be a guru at FPGA & VLSI design and verication?

Upvote 1 Downvote Comment

Fred Diggs, Digital logic designer

Upvote Downvote Comment 1

AnswerwrittenChinaTopicyoumightlikeSun AnswerwrittenLifeandLivingTopicyoumight AnswerwrittenPhotographsTopicyoumightlike

Upvote 10 Downvote Comments 3+

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