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Chap06 (6 24 06) PDF
Chap06 (6 24 06) PDF
0-1
What is an Op Amp?
The op amp (operational amplifier) is a high gain, dc coupled amplifier designed to
be used with negative feedback to precisely define a closed loop transfer function.
The basic requirements for an op amp:
Sufficiently large gain (the accuracy of the signal processing determines this)
Differential inputs
Frequency characteristics that permit stable operation when negative feedback is
applied
Other requirements:
High input impedance
Low output impedance
High speed/frequency
Why Op Amps?
The op amp is designed to be used with single-loop, negative feedback to accomplish
precision signal processing as illustrated below.
Single-Loop Negative Feedback Network Op Amp Implementation of a Single-Loop
Negative Feedback Network
Feedback Network
Vf(s) Vf(s)
F(s) F(s)
Vin(s) + Vout(s) Vout(s)
A(s) Vin(s)
+
Av(s)
Op Amp 060625-01
Vout(s)
The voltage gain, Vin(s) , can be shown to be equal to,
Vout(s) Av(s)
=
Vin(s) 1+Av(s)F(s)
If the product of Av(s)F(s) is much greater than 1, then the voltage gain becomes,
Vout(s) 1
Vin(s) F(s) The precision of the voltage gain is defined by F(s).
R1
- R2
+ + +
vinn +
v2 vout
vinp v1
- - -
Fig. 110-03
Non-inverting voltage amplifier:
R1+R2
vinn = 0 vout = R1 vinp
+ + ii - +
vin vi + vout
- - -
Virtual Ground Fig. 110-04
Solution
If Av , then vi 0 because of the negative feedback path through R2.
(The op amp with fb. makes its input terminal voltages equal.)
vi = 0 and ii = 0
Note that the null port becomes the familiar virtual ground if one of the op amp input
terminals is on ground. If this is the case, then we can write that
vin vout
i1 = R1 and i2 = R2
vout R2
Since, ii = 0, then i1 + i2 = 0 giving the desired result as vin = - R1 .
OP AMP CHARACTERIZATION
Linear and Static Characterization of the CMOS Op Amp
A model for a nonideal op amp that includes some of the linear, static nonidealities:
v1 Ricm
CMRR Cicm en2
v2 * -
Rout vout
VOS Cid Rid
+
v1 Ideal Op Amp
Ricm
Cicm
060625-03
where
Rid = differential input resistance
Cid = differential input capacitance
Ricm = common mode input resistance
CRicm = common mode input capacitance
VOS = input-offset voltage
CMRR = common-mode rejection ratio (when v1=v2 an output results)
e2n = voltage-noise spectral density (mean-square volts/Hertz)
CMOS Analog Circuit Design P.E. Allen - 2006
Chapter 6 Section 1 (6/24/06) Page 6.1-6
Differential-frequency response:
Av0 Av0 p1p2p3
Av(s) = s s
s
= (s -p1)(s -p2)(s -p3)
p
1
- 1
p
2
- 1
p
3
- 1
where p1, p2, p3, are the poles of the differential-frequency response (ignoring zeros).
|Av(j)| dB
Asymptotic
20log10(Av0) Magnitude
Actual -6dB/oct.
Magnitude
GB
2 3
0dB
1
-12dB/oct.
-18dB/oct.
Fig. 110-06
Settling Time
0 t
0 Ts Fig. 110-07
OP AMP CATEGORIZATION
Classification of CMOS Op Amps
Conversion Hierarchy
Current
Voltage Transconductance Transconductance Stage
to Current Grounded Gate Grounded Source
Second
Voltage
Current Class A (Source Class B Stage
to Voltage or Sink Load) (Push-Pull)
Table 110-01
VDD
M3 M4
M6
- vout -
M1 M2 vout
vin vin
+
+
VBias M7
M5
VSS
VI IV VI I V Fig. 6.1-8
VBias
M4 M5
VSS
VI II I V 060118-10
Design Inputs
Boundary conditions:
1. Process specification (VT, K', Cox, etc.)
2. Supply voltage and range
3. Supply current and range
4. Operating temperature and range
Requirements:
1. Gain
2. Gain bandwidth
3. Settling time
4. Slew rate
5. Common-mode input range, ICMR
6. Common-mode rejection ratio, CMRR
7. Power-supply rejection ratio, PSRR
8. Output-voltage swing
9. Output resistance
10. Offset
11. Noise
12. Layout area
M6
M3 M4 Cc
Topology- M1 M2
vout
CL
vin
+
+ M7
VBias M5
-
DC Currents VSS
W/L ratios W
Component C R
values
060625-06
+
Definitions: Vin(s) A(s) Vout(s)
Open-loop gain = L(s) = -A(s)F(s) Fig. 120-01
Vout(s) A(s)
Closed-loop gain = Vin(s) = 1+A(s)F(s)
Stability Requirements:
The requirements for stability for a single-loop, negative feedback system is,
|A(j0)F(j0)| = |L(j0)| < 1
where 0 = 360 is defined as
Arg[A(j0)F(j0)] = Arg[L(j0)] = 0 = 360
Another convenient way to express this requirement is
Arg[A(j0dB)F(j0dB)] = Arg[L(j0dB)] > 0
where 0dB is defined as
|A(j0dB)F(j0dB)| = |L(j0dB)| = 1
|A(j)F(j)|
-20dB/decade
0dB
-40dB/decade
180
Arg[-A(j)F(j)]
225
270
315
M
360 0dB
Frequency (rads/sec.) 060625-07
A measure of stability is given by the phase when |A(j)F(j)| = 1. This phase is called
phase margin.
Phase margin = M = 360 - Arg[-A(j0dB)F(j0dB)] = 360 - Arg[L(j0dB)]
0.2
0
0 5 10 15 Fig. 120-03
ot = nt (sec.)
A good step response is one that quickly reaches its final value.
Therefore, we see that phase margin should be at least 45 and preferably 60 or larger.
(A rule of thumb for satisfactory stability is that there should be less than three rings.)
Note that good stability is not necessarily the quickest risetime.
M3 M4 Q3 Q4
M6 Q6
vout vout
- M1 M2 - Q1 Q2
vin vin
+ +
+ M7 + Q7
VBias M5 VBias Q5
- -
VSS VEE Fig. 120-04
Small-Signal Model:
|A(j)|
GB
0dB log10()
Phase Shift -40dB/decade
-45/decade
180
Arg[-A(j)]
225
-45/decade
270
315
360 log10()
|p1'| |p2'| 0dB 060625-08
If we assume that F(s) = 1 (this is the worst case for stability considerations), then the
above plot is the same as the loop gain.
Note that the phase margin is much less than 45 ( 6).
Therefore, the op amp must be compensated before using it in a closed-loop
configuration.
CMOS Analog Circuit Design P.E. Allen - 2006
MILLER COMPENSATION
Miller Compensation of the Two-Stage Op Amp
VDD VCC
M3 M4
Q3 Q4
CM M6 CM Q6
Cc vout Cc vout
M1 M2 Q1 Q2
- -
vin CI CII vin CI CII
+ +
+ M7 + Q7
VBias M5 VBias Q5
- -
VSS VEE Fig. 120-08
The various capacitors are:
Cc = accomplishes the Miller compensation
CM = capacitance associated with the first-stage mirror (mirror pole)
CI = output capacitance to ground of the first-stage
CII = output capacitance to ground of the second-stage
Cc
v2
+ +
vin gm1vin CI CII vout
rds2||rds4 gm6v2 rds6||rds7
- -
Fig. 120-09
Same circuit holds for the BJT op amp with different component relationships.
p2 p2' p1' p1 z1 Fig. 120-11
F(j)=1 -20dB/decade
Compensated
GB
0dB log10()
Phase Shift -40dB/decade
Uncompensated
180
Arg[-A(j)F(j)|
-45/decade
225
F(j)=1
270 -45/decade
Compensated Phase
315
No phase margin Margin
360 log10()
|p1| |p1'| |p2'| |p2|
060118-10
Note that the unity-gainbandwidth, GB, is
1 gmI gm1 gm2
GB = Avd(0)|p1| = (gmIgmIIRIRII)gmIIRIRIICc = Cc = Cc = Cc
Fig. 120-14
3.) Right-half plane zero (One source VDD
of zeros is from multiple paths from the input to output): Cc
RII
g vout
m6
-g R (1/sC )
m6 II
R
-RIIsCc - 1
M6
vout = RII + 1/sCcc v + RII + 1/sC
II
v =
c RII + 1/sCc v
v''
v'
Fig. 120-15
where v = v = v.
Further Comments on p2
The previous observations on p2 can be proved as follows:
Find the resistance RCc seen by the compensation capacitor, Cc.
Cc VDD
vx
RCc RII
RCc
ix ix
M6 +
RI RI vgs6 RII
gm6vgs6
060626-02
i3 +
gm1Vin gm2Vin Vo1
2 1 i3
rds1 rds3 gm3 C3 2 rds2 rds4 -
Fig. 120-16
The transfer function from the input to the output voltage of the first stage, Vo1(s), can be
written as
Vo1(s) -gm1 gm3+gds1+gds3 -gm1 sC + 2g
3 m3
Vin(s) = 2(gds2+gds4) gm3+ gds1+gds3+sC3 + 1 2(gds2+gds4) sC3 + gm3
GB GB
135 tan-1(Av(0)) + tan-1|p2| + tan-1(0.1) = 90 + tan-1|p2| + 5.7
GB GB
39.3 tan-1|p2| |p2| = 0.818 |p2| 1.22GB
The requirement for 60 phase margin:
|p2| 2.2GB if z 10GB
If 60 phase margin is required, then the following relationships apply:
gm6 10gm1 gm6 2.2gm1
Cc > Cc gm6 > 10gm1 and C2 > Cc Cc > 0.22C2
j
j3 Loop
Gain RHP Zero Boost
j2 0dB log10
180 > 1 > 2 > 3
180
3 Loop
j1 2
1 Phase
Shift
z1 360 log10
060626-03 RHP Zero Lag
Solution of the problem:
The compensation comes from the feedback path through Cc, but the RHP zero
comes from the feedforward path through Cc so eliminate the feedforward path!
Use of Buffer to Eliminate the Feedforward Path through the Miller Capacitor
Model:
Cc
+1 Cc
VI
The transfer + +
function is given Inverting vOUT V in gmIvin CI RI Vout
CII
Vout
gmIIVI RII
by the following High-Gain - -
Stage
Fig. 430-02
equation,
Vo(s) (gmI)(gmII)(RI)(RII)
Vin(s) = 1 + s[RICI + RIICII + RICc + gmIIRIRIICc] + s2[RIRIICII(CI + Cc)]
Using the technique as before to approximate p1 and p2 results in the following
1 1
p1 RICI + RIICII + RICc + gmIIRIRIICc gmIIRIRIICc
and
gmIICc
p2 CII(CI + Cc)
Comments:
Poles are approximately what they were before with the zero removed.
For 45 phase margin, |p2| must be greater than GB
For 60 phase margin, |p2| must be greater than 1.73GB
Use of Buffer with Finite Output Resistance to Eliminate the RHP Zero
Assume that the unity-gain buffer has an output resistance of Ro.
Model:
Cc Ro
+1 Cc
VI
+ Vout +
vOUT Vin gmIvin CI RI Ro Ro Vout
Inverting
gmIIVI RII CII
High-Gain - -
Stage
Fig. 430-03
It can be shown that if the output resistance of the buffer amplifier, Ro, is not neglected
that another pole occurs at,
1
p4 Ro[CICc/(CI + Cc)]
and a LHP zero at
1
z2 RoCc
Closer examination shows that if a resistor, called a nulling resistor, is placed in series
with Cc that the RHP zero can be eliminated or moved to the LHP.
Use of Nulling Resistor to Eliminate the RHP Zero (or turn it into a LHP zero)
Cc Rz
Cc Rz
VI
+ +
vOUT Vin gmIvin CI RI Vout
Inverting CII
gmIIVI RII
High-Gain - -
Stage
Fig. 430-04
Nodal equations:
VI sCc
gmIVin + RI + sCIVI + 1 + sCcRz (VI Vout) = 0
Vo sCc
gmIIVI + RII + sCIIVout + 1 + sCcRz (Vout VI) = 0
Solution:
Vout(s) a{1 s[(Cc/gmII) RzCc]}
Vin(s) = 1 + bs + cs2 + ds3
where
a = gmIgmIIRIRII
b = (CII + Cc)RII + (CI + Cc)RI + gmIIRIRIICc + RzCc
c = [RIRII(CICII + CcCI + CcCII) + RzCc(RICI + RIICII)]
d = RIRIIRzCICIICc
W,J. Parrish, "An Ion Implanted CMOS Amplifier for High Performance Active Filters", Ph.D. Dissertation, 1976, Univ. of CA., Santa Barbara.
CMOS Analog Circuit Design P.E. Allen - 2006
Chapter 6 Section 2 (6/24/06) Page 6.2-21
RII
Cc Rz
Vout
M6
V''
V'
Fig. Fig. 430-05
The output voltage, Vout, can be written as
gm6
1
-gm6R Rz + sCc II
RII -RIIgm6Rz + sCc - 1
Vout = 1 V + 1 V = 1 V
RII + Rz + sCc RII + Rz + sCc RII + Rz + sCc
when V = V = V.
Setting the numerator equal to zero and assuming gm6 = gmII gives,
1
z1 = Cc(1/gmII Rz)
A Design Procedure that Allows the RHP Zero to Cancel the Output Pole, p2
We desire that z1 = p2 in terms of the previous notation.
Therefore,
1 gmII j
Cc(1/gmII Rz) = CII
-p -p -p 1 z Fig. 430-06
The value of Rz can be found as 4 2 1
C + C
c II
Rz = Cc (1/gmII)
With p2 canceled, the remaining roots are p1 and p4(the pole due to Rz) . For unity-gain
stability, all that is required is that
Av(0) gmI
|p4| > Av(0)|p1| = gmIIRIIRICc = Cc
and (1/RzCI) > (gmI/Cc) = GB
Substituting Rz into the above inequality and assuming CII >> Cc results in
gmI
Cc > gmII CICII
This procedure gives excellent stability for a fixed value of CII ( CL).
Unfortunately, as CL changes, p2 changes and the zero must be readjusted to cancel p2.
CMOS Analog Circuit Design P.E. Allen - 2006
B.K. Ahuja, An Improved Frequency Compensation Technique for CMOS Operational Amplifiers, IEEE J. of Solid-State Circuits, Vol. SC-18,
No. 6 (Dec. 1983) pp. 629-633.
CMOS Analog Circuit Design P.E. Allen - 2006
Chapter 6 Section 2 (6/24/06) Page 6.2-25
1 + s gm8 + G2 + G2 + G1G2
+ s2
gm8G2
Using the approximate method of solving for the roots of the denominator gives
-1 -6
p1 = Cc Cc C2 gm6Cc g r 2C
m6 ds c
gm8 + G2 + G2 + G1G2
gm6rds2Cc
6 - gm8rds2G2
gm6
gm8rds
and p2 CcC2 = 6
=
C2 3 |p2|
gm8G2
where all the various channel resistance have been assumed to equal rds and p2 is the
output pole for normal Miller compensation.
Result:
Dominant pole is approximately the same and the output pole is increased by gmrds.
VDD VDD
3 3
Rout = rds7|| gm6gm8r
ds8
gm6gm8rds8
Therefore, the output pole is approximately,
gm6gm8rds8
|p2| 3CII
C2 C2
-A -A
R1 C1 R1 C1 C3(1+A)
RootID01
C2 C2
+A +A
R1 C1 R1 C1 C3(1-A)
RootID02
vin vout
+ A(s)
RootID03
s
1 Vout A(s) A(s) A(s) p1 +1
If F(s) = s , then Vin = 1+A(s)F(s) = 1 =s
p1 +1 1+A(s) s p1 +1+ A(s)
p1 +1
2.) Zeros are also created by two paths VDD
from the input to the output and one of RII
more of the paths is frequency dependent. Cc
vout
M6
v''
v'
Fig. 120-15
Cc
A
+ +
Vi gmIIVi CII RII Vout
- - Fig.430-09
Vout(s) AC s + gmII/ACc
c
Vin(s) = Cc + C s + 1/[RII(Cc + CII)]
II
Self-Compensated Op Amps
Self compensation occurs when the load capacitor is the compensation capacitor (can
never be unstable for resistive feedback)
|dB|
M6 M6
M3 M4 I6 ICL M3 M4 I6=0
Cc I5 Cc I5 ICL
vout vout
- M1 M2 Assume a CL - M1 M2 Assume a CL
vin>>0 virtural I7 vin<<0 virtural I7
+ ground + ground
I5 I5
+ M7 + M7
VBias M5 VBias M5
- -
VSS VSS
Positive Slew Rate Negative Slew Rate Fig. 140-05
I5 I -I -I I I I -I I5
6 5 7 5 5 7 5
SR+ = min Cc, C
= C because I6>>I5
L
c
SR- = min C , C = Cc if I7>>I5.
c L
Therefore, if CL is not too large and if I7 is significantly greater than I5, then the slew
rate of the two-stage op amp should be, I5/Cc.
M6
M3 M4 Cc
vout
- M1 M2 CL
vin
+
+ M7
VBias M5
-
VSS Fig. 6.3-1
Notation:
Wi
Si = Li = W/L of the ith transistor
S7
S7
3.) However, I7 = S5I5 = S5 (2I4)
S6 2S7
4.) For balance, I6 must equal I7 S4 = S5 called the balance conditions
5.) So if the balance conditions are satisfied, then VDG4 = 0 and M4 is saturated.
CMOS Analog Circuit Design P.E. Allen - 2006
Chapter 6 Section 3 (6/24/06) Page 6.3-3
Op Amp Specifications
The following design procedure assumes that specifications for the following parameters
are given.
1. Gain at dc, Av(0) Max. ICMR
and/or p3
2. Gain-bandwidth, GB +
VDD
+
Vout(max)
VSG4 VSG6
3. Phase margin (or settling time) - -
M6 gm6 or
4. Input common-mode range, ICMR M3 M4 Cc I6 Proper Mirroring
5. Load Capacitance, CL g VSG4=VSG6
GB = m1
Cc vout
6. Slew-rate, SR -
Cc 0.2CL CL
vin M1 M2
(PM = 60)
7. Output voltage swing +
DESIGN EXAMPLE
Example 6.3-1 - Design of a Two-Stage Op Amp
Using the material and device parameters given in Tables 3.1-1 and 3.1-2, design an
amplifier similar to that shown in Fig. 6.3-1 that meets the following specifications.
Assume the channel length is to be 1m and the load capacitor is CL = 10pF.
Av > 3000V/V VDD = 2.5V VSS = -2.5V
GB = 5MHz SR > 10V/s 60 phase margin
Vout range = 2V ICMR = -1 to 2V Pdiss 2mW
Solution
1.) The first step is to calculate the minimum value of the compensation capacitor Cc,
Cc > (2.2/10)(10 pF) = 2.2 pF
2.) Choose Cc as 3pF. Using the slew-rate specification and Cc calculate I5.
I5 = (3x10-12)(10x106) = 30 A
3.) Next calculate (W/L)3 using ICMR requirements.
30x10-6
(W/L)3 = (50x10-6)[2.5 2 .85 + 0.55]2 = 15 (W/L)3 = (W/L)4 = 15
VDD = 2.5V
M3 M4 M6
15m 15m 94m
1m 1m 1m
Cc = 3pF
vout
30A M1 M2
- 3m 3m CL =
1m 1m 95A 10pF
vin
+
30A
4.5m 14m
1m 4.5m 1m
M8 M5 1m M7
Fig. 6.3-3
VSS = -2.5V
CMOS Analog Circuit Design P.E. Allen - 2006
Chapter 6 Section 3 (6/24/06) Page 6.3-13
M11 M3 M4 V
B
VA M6
M10 CM Cc vout
M8
VC vin- vin+
M1 M2
CL
IBias
M9 M5
M12 M7
K1IBias M5
M7
SR = Cc IBias
VSS Fig. 6.3-04D
1 1 103
Rout = 2K2IBias IBias Pdiss and SR |p1|
102
1 IBias2
|p1| = gmIIRIRIICc I IBias1.5 101
Bias GB and z
100
gmII 10-1
|z| = Cc IBias Ao and Rout
10-2
Illustration of the Ibias dependence
10-3
1 10 100
IBias Fig. 160-05
IBias(ref)
CMOS Analog Circuit Design P.E. Allen - 2006
Chapter 6 Section 3 (6/24/06) Page 6.3-19
Poly W
Diffusion Diffusion
L Fig. 6.3-5
Av(Vdd=0) V2 - VDD
PSRR = Add(Vin=0)
Vout
Vin V1 +
Vss VSS
How do you calculate PSRR?
You could calculate Av and Add and divide, Fig.180-01
however
Vdd
V2
V2 - VDD Av(V1-V2)
Vout V1 Vout
V1 +
Vss VSS AddVdd
Fig. 180-02
Vout = AddVdd + Av(V1-V2) = AddVdd - AvVout Vout(1+Av) = AddVdd
Vout Add Add 1
V
dd
= 1+A v
A =
v PSRR+
(Good for frequencies up to GB)
CMOS Analog Circuit Design P.E. Allen - 2006
Chapter 6 Section 3 (6/24/06) Page 6.3-21
Vout
M6 VDD Vdd 1
Cc Vout RoutCc
M3 M4 Cc Vout 0dB
M5 rds7
M7 Vss Path through Cgd7
VBias
is negligible
What is Zout? VSS
VBias connected to VSS
Vt Fig. 180-11
Zout = It
Cc CII+Cgd7 It
gmIVt
It = gmIIV1 = g mII GI+sCI+sCc + rds6||rds7 +
CI RI V1 gmIIV1 Vout Vt
GI+s(CI+Cc) gmIVout
- -
Thus, Zout = gmIgMII Fig.180-12
rds7
Vout 1+ Zout s(Cc+CI) + GI+gmIgmIIrds7 -GI
Vss = 1 = s(Cc+CI) + GI Pole at Cc+CI
The negative PSRR is much better than the positive PSRR.
CMOS Analog Circuit Design P.E. Allen - 2006
Chapter 6 Section 4 (6/24/06) Page 6.4-1
MB5
MC1 MC2 MC1 + MC2
M1 M2 M1 VBias M2
VBias MB1 MB2
+v - +v
in vin in - vin -
2- + 2 2- + 2
+ M5 + M5
VNBias1 VNBias1
- -
VSS VSS 060627-01
M7 M8 M7 M8
M15
-A M5 M6
VNB1
M5 M6 M16
vOUT VDD VDD vOUT
VPB1
M3 M4
M13 M14
-A -A M3 M4
M11 M12
M1 M2 M1 M2
+ +
vIN vIN
M9
VNB1 M9 VNB1 M10
060627-02
Av = gmIgmIIRIRII VDD
where gmI = gm1 = gm2, gmII = gm6,
M6
M3 M4
1 2
RI = gds2 + gds4 = (2 + 4)ID5
VBP MC6
Rz Cc
vout
and
- M1 M2 VBN MC7 CL
vin
RII = (gmC6rdsC6rds6)||(gmC7rdsC7rds7) +
+ M7
VBias M5
-
VSS Fig. 6.5-3
Comments:
The second-stage gain has greatly increased improving the Miller compensation
The overall gain is approximately (gmrds)3 or very large
Output pole, p2, is approximately the same if Cc is constant
The zero RHP is the same if Cc is constant
PSRR is poor unless the Miller compensation is removed (then the op amp becomes
self compensated)
CMOS Analog Circuit Design P.E. Allen - 2006
Chapter 6 Section 4 (6/24/06) Page 6.4-7
vout where
- M1 M2
VNB2 M9 RII = (gm7rds7rds6)||(gm12rds12rds11)
vin M12 CL
+ and
M5 M10
+ M11 gm8 gm6
VNB1
-
k = gm3 = gm4
VSS
060627-03
This op amp is balanced because the drain-to-ground loads for M1 and M2 are identical.
;;;
Technological Implications of the Cascode Configuration
A
A B C D
;;;;;;;
B Thin
oxide Poly I Poly II
n+ n-channel n+
C p substrate/well
D
Fig. 6.5-5
If a double poly CMOS process is available, internode parasitics can be minimized.
;;
As an alternative, one should keep the drain/source between the transistors to a minimum
area.
Minimum Poly
A separation
A B C D
;;;;;;;;
B Thin
oxide Poly I Poly I
n+ n-channel n+ n-channel n+
C p substrate/well
D
Fig. 6.5-5A
Input Common Mode Range for Two Types of Differential Amplifier Loads
VDD-VSD3+VTN
VDD VDD
VDD-VSG3+VTN
+ + + +
VSG3 VSD4 VSD3 VSD4
Input
Input
- M3 M4 - Common - M3 M4 -
VBP
Common Mode
Mode Range
Range M1 M2 M1 M2
VSS+VDS5+VGS1 VSS+VDS5+VGS1
+ M5 vicm + M5 vicm
VBias VBias
- -
VSS VSS
Differential amplifier with Differential amplifier with
a current mirror load. current source loads. Fig. 6.5-6
In order to improve the ICMR, it is desirable to use current source (sink) loads without
losing half the gain.
The resulting solution is the folded cascode op amp.
RA VPB2 RB
I1 I2
I6 I7
vOUT
M6 M7
M1 M2 VNB2
+
vIN
M8 M9 CL
M3
VNB1 I3 M11
M10
Comments: 060628-04
I4 and I5, should be designed so that I6 and I7 never become zero (i.e. I4=I5=1.5I3)
This amplifier is nearly balanced (would be exactly if RA was equal to RB)
Self compensating
Poor noise performance, the gain occurs at the output so all intermediate transistors
contribute to the noise along with the input transistors. (Some first stage gain can be
achieved if RA and RB are greater than gm1 or gm2.
=
RII(gds2+gds5) 2(1+k) where k = gm7rds7
2 gm7rds7 + (rds2||rds5)
2
1 +
gm7rds7
The output voltage, vout, is equal to the sum of i7 and i10 flowing through Rout. Thus,
vout
gm1 gm2 2+k
=
Vss
Fig. 6.5-9A
This model assumes that gate, source and drain of M11 and the gate and source of M9 all
vary with VSS.
We shall examine Vout/Vss rather than PSRR-. (Small Vout/Vss will lead to large PSRR-.)
The transfer function of Vout/Vss can be found as
Vout sCgd9Rout
Vss sCoutRout+1 for Cgd9 < Cout
The approximate PSRR- is sketched on the next page.
dB
|PSRR-|
|Avd()|
1
Cgd9Rout
Dominant
pole frequency
0dB log10()
Cgd9 GB
Cout
Vout Fig. 6.5-10A
Vss
Other sources of Vss injection, i.e. rds9
We see that the PSRR of the cascode op amp is much better than the two-stage op amp.
The value of 0.5(Vout(min)-|VSS|) is also 0.25V which gives the value of S8, S9, S10 and
2I8 2125
S11 as S8 = S9 = S10 = S11 = K V 2 = 110(0.25)2 = 36.36
N DS8
CMOS Analog Circuit Design P.E. Allen - 2006
We need to check that the values of S4 and S5 are large enough to satisfy the maximum
input common mode voltage. The maximum input common mode voltage of 2.5 requires
2I4 2125A
S4 = S5 K [V -V (max)+V ]2 = 50x10-6A/V2[0.7V]2 = 10.2
P DD in T1
which is much less than 80. In fact, with S4 = S5 = 80, the maximum input common
mode voltage is 3V.
The power dissipation is found to be
Pdiss = 5V(125A+125A) = 1.25mW
-A -A
VNB1 M4
M5
Voltage gain = gm1Rout,
060718-03
where
Rout [Ards7gm7(rds1||rds5)]|| (Ards9gm9rds11)
Since A gmrds the voltage gain would be in the range of 100,000 to 500,000.
Note that to achieve maximum output swing, it will be necessary to make sure that M5
and M11 are biased with VDS = VDS(sat).
CMOS Analog Circuit Design P.E. Allen - 2006
0dB log10
|p1(enh)| |p1| GB 060629-02
VDD
vIN vOUT
CL RL VSS
C R
Fig. 240-02
Resulting Closed-Loop Frequency Response:
dB Op Amp
Av(0) Open Loop
Frequency
Response
0dB log10(w)
1 Av(0)
RC RC Fig. 240-03
R
R VDD
vIN vOUT
+
vi
CL RL VSS
-
Fig. 240-04
Make R as large and measure vout and vi to get the open loop gain.
V
+ OS- VDD
vout
+
vcm VSS
- CL RL
Fig. 6.6-5
Make sure that the output voltage of the op amp is in the linear region.
Fig. 6.6-7
V1+V
2
Vout = Av(V1-V2) A
cm 2 = -AvVout AcmVcm
Acm Acm
Vout = 1+Av Vcm Av Vcm
Av Vcm
|CMRR| = Acm = Vout
- VDD Av(V1-V2)
V2
V1 + V1 Vout
Vss = 0
Vss VSS
AddVdd
Fig. 6.6-9
Vout = Av(V1-V2) AddVdd = -AvVout AddVdd
Add Add
Vout = 1+Av Vdd Av Vdd
Av Vdd Av Vss
PSRR+ = Add = Vout and PSRR- = Ass = Vout
However, in the above circuit the value of vout is the same so that we get
vicm
CMRR = vid
vos
But vid = vi and vos 1000vi = 1000vid vid = 1000
vicm 1000 vicm
Substituting in the previous expression gives, CMRR = vos = vos
1000
VDD
Vout
+
10 Vi
- CL RL VSS
060701-01
Vout Vout
Avd = Vid = Vi
Vos 1000Vi
1000Vout
Therefore, Avd = Vos
IDD 1
VDD
vOUT 1
+ vIN
vIN ICMR
- VSS
CL RL
ISS
Also, monitor
IDD or ISS. Fig.240-11
Initial jump in sweep is due to the turn-on of M5.
Should also plot the current in the input stage (or the power supply current).
Overshoot (%)
50
10
0 0.1
0 0.2 0.4 0.6 0.8 1
= 1 Fig. 240-15
2Q
.SUBCKT OPAMP 1 2 6 8 9
M1 4 2 3 3 NMOS1 W=3U L=1U AD=18P AS=18P PD=18U PS=18U
M2 5 1 3 3 NMOS1 W=3U L=1U AD=18P AS=18P PD=18U PS=18U
M3 4 4 8 8 PMOS1 W=15U L=1U AD=90P AS=90P PD=42U PS=42U
M4 5 4 8 8 PMOS1 W=15U L=1U AD=90P AS=90P PD=42U PS=42U
M5 3 7 9 9 NMOS1 W=4.5U L=1U AD=27P AS=27P PD=21U PS=21U
M6 6 5 8 8 PMOS1 W=94U L=1U AD=564P AS=564P PD=200U PS=200U
M7 6 7 9 9 NMOS1 W=14U L=1U AD=84P AS=84P PD=40U PS=40U
M8 7 7 9 9 NMOS1 W=4.5U L=1U AD=27P AS=27P PD=21U PS=21U
CC 5 6 3.0P
.MODEL NMOS1 NMOS VTO=0.70 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
+MJ=0.5 MJSW=0.38 CGBO=700P CGSO=220P CGDO=220P CJ=770U CJSW=380P
+LD=0.016U TOX=14N
.MODEL PMOS1 PMOS VTO=-0.7 KP=50U GAMMA=0..57 LAMBDA=0.05 PHI=0.8
+MJ=0.5 MJSW=.35 CGBO=700P CGSO=220P CGDO=220P CJ=560U CJSW=350P +LD=0.014U TOX=14N
IBIAS 8 7 30U
.ENDS
2.5
2
VOS
1
vOUT(V)
-1
-2
-2.5
-2 -1.5 -1.0 -0.5 0 0.5 1 1.5 2
vIN(mV) Fig. 240-18
80 200
150
60
Phase Shift (Degrees)
100
Magnitude (dB)
40
50
20 0
-50
0
-100
-20
-150 Phase Margin
GB GB
-40 -200
10 100 1000 104 105 106 107 108 10 100 1000 104 105 106 107 108
Frequency (Hz) Frequency (Hz) Fig. 6.6-16
ID(M5) A
3 30
..
.
.DC VIN+ -2.5 2.5 0.1 2 20
Input CMR
vOUT (V)
.PRINT DC V(3)
1 10
.TRAN 0.05U 10U 0 10N
.PRINT TRAN V(3) V(1) 0 0
.AC DEC 10 1 10MEG
.PRINT AC VDB(3) VP(3) -1
.PROBE (This entry is unique to PSPICE)
.END -2
-3
-3 -2 -1 0 1 2 3
vIN(V) Fig. 240-21
100 100
80
Arg[PSRR+(j)] (Degrees)
50
|PSRR+(j)| dB
60
40 0
20
-50
0
-20 -100
10 100 1000 104 105 106 107 108 10 100 1000 104 105 106 107 108
Frequency (Hz) Frequency (Hz) Fig. 240-22
120 200
150
Arg[PSRR-(j)] (Degrees)
100
100
|PSRR-(j)| dB
80 50
0
60 -50
PSRR+
-100
40
-150
20 -200
10 100 1000 104 105 106 107 108 10 100 1000 104 105 106 107 108
Frequency (Hz) Frequency (Hz) Fig. 240-23
1 0.1 vin(t)
0.5 0.05
vout(t)
vout(t)
Volts
Volts
0 0
-0.5 -0.05
vin(t)
-1 -0.1
-1.5 -0.15
2.5 3.0 3.5 4.0 4.5
0 1 2 3 4 5
Time (Microseconds) Time (Microseconds) Fig. 240-24
Op Amp Characterization
Small signal, frequency independent
Small signal, frequency dependent
Large signal
Time independent
Time dependent
v1
vo 1 Ro v o 1 vo
A R id Avd (v 1 -v 2 ) R id Avd (v -v ) Ro
2 2 Ro 1 2
v2
v2 v2
(a.) (b.) (c.) Fig. 010-01
Figure 1 - (a.) Op amp symbol. (b.) Thevenin form of simple model. (c.) Norton form of
simple model.
SPICE Description of Fig. 1c Subcircuit SPICE Description for Fig. 1c
RID 1 2 {Rid} .SUBCKT SIMPLEOPAMP 1 2 3
RO 3 0 {Ro} RID 1 2 {Rid}
GAVD 0 3 1 2 {Avd/Ro} RO 3 0 {Ro}
GAVD 0 3 1 2 {Avd/Ro}
.ENDS SIMPLEOPAMP
3
Ric1 +
Rid Avc v1 Avc v2
2 Avd(v1 -v2 ) 2Ro 2Ro Ro vo
Ro
-
Ric2
Linear Op Amp Macromodel
Fig. 010-03
Figure 3 - Simple op amp model including differential and common mode behavior.
SPICE File: GAVD/RO 0 3 1 2 {Avd/Ro}
.SUBCKT LINOPAMP 1 2 3 GAVC1/RO 0 3 1 0 {Avc/2Ro}
RIC1 1 0 {Ric} GAVC2/RO 0 3 2 0 {Avc/2Ro}
RID 1 2 {Rid} RO 3 0 {Ro}
RIC2 2 0 {Ric} .ENDS LINOPAMP
Example 2
VIN 1 0 DC 0 AC 1 R12 32 0 1KOHM GAVD/RO 0 3 1 2 1000
*Unity Gain Configuration R22 22 32 9KOHM R1 3 0 100
XOPAMP1 1 31 21 *Gain of 100 Configuration C1 3 0 100UF
LINFREQOPAMP XOPAMP3 1 33 23 .ENDS
R11 31 0 15GOHM LINFREQOPAMP .AC DEC 10 100 10MEG
R21 21 31 1OHM R13 33 0 1KOHM .PRINT AC V(21) V(22) V(23)
*Gain of 10 Configuration R23 23 33 99KOHM .PROBE
XOPAMP2 1 32 22 .SUBCKT .END
LINFREQOPAMP LINFREQOPAMP 1 2 3
RID 1 2 1MEGOHM
20dB Gain of 10
10dB
Gain of 1
0dB
-10dB
15.9kHz 159kHz 1.59MHz
-20dB
100Hz 1kHz 10kHz 100kHz 1MHz 10MHz
Fig. 010-06
Figure 6 - Frequency response of the three noninverting voltage amplifiers of Ex. 6.6-2.
Avc v1 Avc v2
1 2Ro 2Ro C2 R2
Feedforward:
A (0)
vd
Vo(s) = (s/1) +1[1+k(s/1)+k] [V1(s)-V2(s)] .
1
The zero can be expressed as z1 = -11 + k
where k can be + or - by reversing the direction of the current source.
80dB
VDB(2)
60dB
40dB
15.9Hz or 100rps
20dB
1.59MHz or 10Mrps
0dB
1Hz 10Hz 100Hz 1kHz 10kHz 100kHz 1MHz 10MHz
Frequency Fig. 010-09
Figure 9 - Asymptotic magnitude frequency response of the op amp model of Ex. 6.6-3.
7.5V
5V
2.5V
V(2) 0V
-2.5V
-5V
-7.5V
-10V -5V 0V 5V 10V
VIN Fig. 010-11
Figure 11 - Simulation results for Ex. 6.6-4.
Io D1 D3 Io
ILimit
ILimit D2 D4 ILimit
2 2
Io Io
2 2 Fig. 010-12
Macromodel for Output Voltage and Current Limiting:
v1
5
4 D3 D1 3
1
vo
Rid D5 D6
2 D4 D2 7 8
Avd Ro + +
v2 (v -v ) ILimit 6 VOH VOL
Ro 1 2 - -
Fig. 010-13
5V
V(3)
0V
-5V
-10V
-15V -10V -5V 0V 5V 10V 15V
VIN Fig. 010-14
Figure 14 - Results of Example 6.6-5.
5V
Output
Voltage
0V
-5V
Input
Voltage
-10V
0s 2s 4s 6s 8s 10s
Time Fig. 010-16
Figure 16 - Results of Ex. 6.6-6 on modeling the slew rate of an op amp.