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ECE357: Introduction to VLSI CAD

c o m
ld .
o r
t u w
jn
Prof. Hai Zhou
w .
Electrical Engineering & Computer Science
w w Northwestern University
www.specworld.in 1 www.smartzworld.com
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Logistics
Time & Location: MWF 11-11:50 TECH L160
c o m
.
Instructor: Hai Zhou haizhou@ece.northwestern.edu
ld
Office: L461
o r
Office Hours: W 3-5P
t u w
. jn
Teaching Assistant: Chuan Lin
w
Texts:
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VLSI Physical Design Automation: Theory & Practice, Sait
& Youssef, World Scientific, 1999.
Reference:
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c o m
An Introduction to VLSI Physical Design, Sarrafzadeh &
Wong, McGraw Hill, 1996.
ld .
r
Grading: Participation-10% Project-30% Midterm-30%
o
Homework-30%
t u w
late: -40% per day
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Homework must be turned in before class on each due date,
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Course homepage:
www.ece.northwestern.edu/~haizhou/ece357
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What can you expect from the course
o m
Understand modern VLSI design flows (but not the details
c
of tools)
ld .
o r
Understand the physical design problem
t u w
Familiar with the stages and basic algorithms in physical
design
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w
problems
w
Improve your capability to design algorithms to solve
Improve your capability to think and reason
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What do I expect from you
Active and critical participation
c o m
yours
ld .
speed me up or slow me down if my pace mismatches
o r
Your role is not one of sponges, but one of whetstones;
t u w
only then the spark of intellectual excitement can
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continue to jump over
w
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Read the textbook
Do your homeworks
You can discuss homework with your classmates, but
need to write down solutions independently
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VLSI (Very Large Scale Integrated) chips
c o m
VLSI chips are everywhere
ld .
computers
o r
t u w
commercial electronics: TV sets, DVD, VCR, ...
automobiles
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voice and data communication networks
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VLSI chips are artifacts
they are produced according to our will ...
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Design: the most challenging human activity
c o m
.
Design is a process of creating a structure to fulfill a
ld
requirement
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t u w
Brain power is the scarcest resource
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Delegate as much as possible to computersCAD
Avoid two extreme views:
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Everything manual: impossiblemillions of gates
Everything computer: impossible either
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Design is always difficult
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A main task of a designer is to manage complexity
c
ld .
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Silicon complexity: physical effects no longer be ignored
o
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resistive and cross-coupled interconnects; signal
integrity; weak and faster gates
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reliability; manufacturability
w
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System complexity: more functionality in less time
gap between design and fabrication capabilities
desire for system-on-chip (SOC)
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CAD: A tale of two designs
c o m
Targethardware design
ld .
o r
How to create a structure on silicon to implement a
function
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Aidsoftware design (programming)
w
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How to create an algorithm to solve a design problem
Be conscious of their similarities and differences
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Emphasis of the course
Design flow
c o m
ld .
Understand how design process is decomposed into
many stages
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What are the problems need to be solved in each stage
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Algorithms
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Understand how an algorithm solves a design problem
Consider the possibility to extend it
Be conscious and try to improve problem solving skills
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Basics of MOS Devices
The most popular VLSI technology: MOS

(Metal-Oxide-Semiconductor).
c o m
CMOS (Complementary MOS) dominates nMOS and
ld .
regularity, etc. o r
pMOS, due to CMOSs lower power dissipation, high
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jn
Physical structure of MOS transistors and their schematic
.
icons: nMOS, pMOS.
w
w w
Layout of basic devices:
CMOS inverter
CMOS NAND gate
CMOS NOR gate
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MOS Transistors gate

drain source
conductor (polysilicon)
insulator (SiO2)
gate
c o m
n n
drain
ld .
substrate
source
psubstrate
ntransistor
diffusion
o r schematic icon
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The nMOS switch passes "0" well.
t
jn
gate
w . drain source
conductor (polysilicon)
insulator (SiO2)
gate
w w p p
drain
substrate
source
nsubstrate diffusion
schematic icon
ptransistor
The pMOS switch passes "1" well.
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A CMOS Inverter
Metal Metaldiffusion contact
A B
VDD pMOS transistor
c o m1 0
ld
nMOS transistor
. 0 1
Polysilicon
o r VDD
A B
t u w pchannel (pMOS)
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Diffusion
A B
w
GND
w nchannel (nMOS)
GND
layout
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A CMOS NAND Gate

A B C
VDD
Metal 0
0
c
0 1
o
1 1m
Diffusion
ld
1
1. 0 1
1 0
Polysilicon
w or VDD
tu
C
A
. j n B
A C
w w B
GND
w GND
layout
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A CMOS NOR Gate

Metal A B C
VDD
0
0
0 1
c o
1 0 m
Polysilicon
ld .1
1
0 0
1 0
wB or VDD
tu
A C
w j. n A
C B
GND w w Diffusion
GND
layout
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Current VLSI design phases
Synthesis (i.e. specification implementation)
c o m
.
1. High level synthesis (459 VLSI Algorithmics)
ld
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2. Logic synthesis (459 VLSI Algorithmics)
o
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3. Physical design (This course)
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Analysis (implementation semantics)
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Verification (design verification, implementation
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verification)
Analysis (timing, function, noise, etc.)
Design rule checking, LVS (Layout Vs. Schematic)
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Physical Design
o
Physical design converts a structural description into a
c m
geometric description.
ld .
Physical design cycle:
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1. Circuit partitioning
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2. Floorplanning
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3. placement, and pin assignment
4. Routing (global and detailed)
5. Compaction
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Design Styles
Issues of
VLSI circuits
c o m
ld .
Performance Area
o r Cost Timetomarket
t u w
w . jn Different design styles
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Full custom Standard cell Gate array FPGA CPLD SPLD SSI
Performance, Area efficiency, Cost, Flexibility
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Full Custom Design Style
c o m
Data path
ld . overthecell
or
PLA routing
I/O
ROM/RAM
tu w
n
via
j
Controller (contact)
w .
w w A/D converter
Random logic
pins I/O pads
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Standard Cell Design Style
D A B
C
c o m
B B
ld .
r
A
D C
w
D o A
t u
w . jnA B
B
w w Cell A Cell B
library cells
Cell C Cell D Feedthrough Cell
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Gate Array Design Style
c o m
ld .
I/O pads
pins
o r
t u w
jn
prefabricated customized
transistor
.
wiring
array
w w
w
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FPGA Design Style
c o m
ld .
o r
t u w
logic
blocks
w . jn routing
tracks
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switches
Prefabricated all chip components
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SSI/SPLD Design Style

x1 y1 x2 y2 x3 y3 x4 y4
m
74LS86 74LS02 74LS00
o
x1 Vcc Vcc Vcc
c
y1 x3
x2
y2
y3
x4
ld .
r
y4
o
GND GND GND
4
F= i=1 xi yi
w
F
(a) 4bit comparator. (b) SSI implementation.
t u
jn
x1
y1
x2
y2
x3
y3
w . AND array
x1 y1 x2 y2
w w
x4
y4
OR array
x3
y3
x4
y4
F
(c) SPLD (PLA) implementation. (d) Gate array implementation.
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c o m
Comparisons of Design Styles
ld .
Full Standard
o r Gate
Cell size
Cell type
custom
variable
variable
t
cell
u
fixed height
variable w array
fixed
fixed
FPGA
fixed
programmable
SPLD
fixed
programmable
Cell placement
Interconnections
variable
w .
variable
jnin row
variable
fixed
variable
fixed
programmable
fixed
programmable
w
* Uneven height cells are also used.
w
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Comparisons of Design Styles

c o m
Full
ld
Standard
.Gate
Fabrication time
Packing density
custom

+++
o r cell

++
array
+
+
FPGA
+++

SPLD
++

Unit cost in large quantity
Unit cost in small quantity
t u
+++
w ++

+
+

+++

+
jn
Easy design and simulation ++ +
Easy design change
.
Accuracy of timing simulation
Chip speed
w

+++

++

+

++
+

++
+

+ desirable
not desirable
w w
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Design-Style Trade-offs
4
10
Full
c o m custom
10
3
ld . semi
custom
o r
10
2
t u w
jn
Turnaround
Time
(Days)
10
w . SPLDs
CPLDs
FPGAs
w w 1
SSIs optimal
solution
2 3 4 5 6 7
1 10 10 10 10 10 10 10
Logic Capacity (Gates)
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Algorithms 101
c o m
ld .
Algorithm: a finite step-by-step procedure to solve a
problem
o r
Requirements:
t u w
. jn
Unambiguity: can even be followed by a machine
w
w w
Basic: each step is among a given primitives
Finite: it will terminate for every possible input
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A game
c o m
ld .
An ECE major is sitting on the Northwestern beach and
r
gets thirsty, she knows that there is an ice-cream booth
o
t u w
along the shore of Lake Michigan but does not know
wherenot even north or south. How can she find the
. jn
booth in the shortest distance?
w
w w
Primitives: walking a distance, turning around, etc.
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A first solution
c o m
ld .
Select a direction, say north, and keep going until find the
booth
o r
t u w
w . jn
Suppose the booth is to the south, she will never stop... of
w w
course, with the assumption she follows a straight line, not
lake shore or on earth
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Another solution
Set the place she is sitting as the origin

c o m
ld .
Search to south 1 yard, if not find, turn to north
o r
t u w
Search to north 1 yard, if not find, turn to south
w . jn
Search to south 2 yard, if not find, turn to north
Search to north 2 yard, if not find, turn to south
w w
... (follow the above pattern in geometric sequence 1, 2, 4,
8, ...)
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OR
c o m
ld .
n = 1;
o r
While (not find) do
t u w
n = n + 1;
w . jn
Search to south 2n, and turn;
w w
Search to north 2n, and turn;
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Correctness proof
c o m
ld .
Each time when the while loop is finished, the range from
south 2n to north 2n is searched. Based on the fact that
o r
the booth is at a constant distance x from the origin, it will
t u w
be within a range from south 2N to north 2N for some N .
jn
With n to increment in each loop, we will find the booth in
finite time.
w .
w w
Is this the fastest (or shortest) way to find the booth?
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Analysis of algorithm
Observation: the traveled distance depends on where is the

booth
c o m
ld .
r
Suppose the distance between the booth and the origin is x
o
2n1 < x
t u w
When the algorithm stops, we should have 2n x but
w . jn
The distance traveled is
w w
3 2n + 2(2 2n1 + 2 2n2 + + 2) 7 2n
which is smaller than 14x
We know that the lower bound is x, can we do better?

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Complexity of an algorithm
Two resources: running time and storage

c o m
ld .
input size
o r
They are dependent on inputs: expressed as functions of
t u w
Why input size: lower bound (at least read it once)
. jn
Big-Oh notation: f (n) = O(g(n)) if there exist constants n0
w
w w
and c such that for all n > n0, f (n) c g(n).
Make our life easy: is it 13x instead of 14x in our game
The solution is asymptotically optimal for our game
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Time complexity of an algorithm
c o m
Run-time comparison: 1000 MIPS (Yr: 200x), 1 instr. /op.
ld .
Time
500
Big-Oh
O(1)
n = 10
5 107 sec
o r
n = 100
5 107 sec
n = 103
5 107 sec
n = 106
5 107 sec
3n
n log n
O(n)
O(n log n)
3 108 sec
t u
3 108 sec w
3 107 sec
2 107 sec
3 106 sec
3 106 sec
0.003 sec
0.006 sec
jn
n2 O(n2 ) 1 107 sec 1 105 sec 0.001 sec 16.7 min
n3
2n
n!
O(n3 )
O(2n )
O(n!)
w . 1 106 sec
1 106 sec
0.003 sec
0.001 sec
3 1017 cent.
-
1 sec
-
-
3 105 cent.
-
-
w w
Polynomial-time complexity: O(p(n)), where n is the input
size and p(n) is a polynomial function of n.
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Complexity of a problem
Given a problem, what is the running time of the fastest

algorithm for it?
c o m
ld .
Upper bound: easyfind an algorithm with less time
o r
Lower bound: hardevery algorithm requires more time
t u w
P: set of problems solvable in polynomial time
w . jn
NP(Nondeterministic P): set of problems whose solution
w w
can be proved in polynomial time
Millennium open problem: NP 6= P?

Fact: there are a set of problems in NP resisting any
polynomial solution for a long time (40 years)
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NP-complete and NP-hard
c o m
ld .
Cook 1970: If the problem of boolean satisfiability can be
o r
solved in poly. time, so can all problems in NP.
t u w
Such a problem with this property is called NP-hard.
. jn
If a NP-hard problem is in NP, it is called NP-complete.
w
w w
Karp 1971: Many other problems resisting poly. solutions
are NP-complete.
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How to deal with a hard problem
Prove the problem is NP-complete:
c o m
poly. time)
ld .
1. The problem is in NP (i.e. solution can be proved in
o r
2. It is NP-hard (by polynomial reducing a NP-complete
problem to it)
t u w
.
Solve NP-hard problems:
w jn
w w
Exponential algorithm (feasible only when the problem
size is small)
Pseudo-polynomial time algorithms
Restriction: work on a subset of the input space
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c o m
Approximation algorithms: get a provable
ld .
close-to-optimal solution
o r
u w
Heuristics: get a as good as possible solution
t
. jn
Randomized algorithm: get the solution with high
probability
w
w w
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Algorithmic Paradigms
Divide and conquer: divide a problem into sub-problems,

solve sub-problems, and combine them to construct a
c o m
solution.
ld .
o r
Greedy algorithm: optimal solutions to sub-problems will
give optimal solution to the whole problem.
t u w
Dynamic programming: solutions to a larger problem are
. jn
constructed from a set of solutions to its sub-problems.
w
Mathematical programming: a system of optimizing an
w w
objective function under constraints functions.
Simulated annealing: an adaptive, iterative,

non-deterministic algorithm that allows uphill moves to
escape from local optima.
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c o m
ld .
o r
t u w
Branch and bound: a search technique with pruning.
w . jn
Exhaustive search: search the entire solution space.
w w
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ECE357: Introduction to VLSI CAD

Time & Location: MWF 11-11:50 TECH L160

What can you expect from the course

Improve your capability to think and reason

What do I expect from you

Active and critical participation

VLSI (Very Large Scale Integrated) chips

Design: the most challenging human activity

Avoid two extreme views:

Design is always difficult

CAD: A tale of two designs

Be conscious of their similarities and differences

Emphasis of the course

Be conscious and try to improve problem solving skills

Basics of MOS Devices

The most popular VLSI technology: MOS

MOS Transistors gate

A CMOS NAND Gate

A CMOS NOR Gate

Current VLSI design phases

Synthesis (i.e. specification implementation)

Performance, Area efficiency, Cost, Flexibility

Full Custom Design Style

pins I/O pads

Standard Cell Design Style

Cell C Cell D Feedthrough Cell

Gate Array Design Style

FPGA Design Style

SSI/SPLD Design Style

Comparisons of Design Styles

Logic Capacity (Gates)

Set the place she is sitting as the origin

Search to north 2 yard, if not find, turn to south

Observation: the traveled distance depends on where is the

which is smaller than 14x

We know that the lower bound is x, can we do better?

Two resources: running time and storage

Time complexity of an algorithm

Given a problem, what is the running time of the fastest

Millennium open problem: NP 6= P?

NP-complete and NP-hard

How to deal with a hard problem

Prove the problem is NP-complete:

Divide and conquer: divide a problem into sub-problems,

Simulated annealing: an adaptive, iterative,

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