TOPIC: 8259 - PROGRAMMABLE INTERRUPT CONTROLLER

with 8086

NAME: JAYALAKSHMI.S

REG.NO:113015045

SEC: B

SOURCE: THE INTEL MICROPROCESSORS ,

WIKIPEDIA, GOOGLE IMAGES

INTRODUCTION

The Intel 8259A Programmable Interrupt Controller handles up to eight vectored priority interrupts for the
CPU.
It is cascadable for up to 64 vectored priority interrupts without additional circuitry. It is packaged in a 28-
pin
DIP, uses NMOS technology and requires a single a5V supply. Circuitry is static, requiring no clock input.

The 8259A is designed to minimize the software and real time overhead in handling multi-level priority
interrupts.
It has several modes, permitting optimization for a variety of system requirements.
The 8259A is fully upward compatible with the Intel 8259. Software originally written for the 8259 will
operate
the 8259A in all 8259 equivalent modes (MCS-80/85, Non-Buffered, Edge Triggered.
 PIN CONFIGURATION

TABLE 1: PIN DESCRIPTION

SYMBOL PIN TYPE DESCRIPTION

NO
Vcc 28 I SUPPLY: +5V SUPPLY
GND 14 I GROUND
1 I CHIP SELECT: A low on this pin enables RD and WR
CS communication
between the CPU and the 8259A. INTA functions are
independent of cs
2 I WRITE: A low on this pin when CS is low enables the
WR 8259A to accept
command words from the CPU.
3 I READ: A low on this pin when CS is low enables the
RD 8259A to release
Status onto the data bus for the CPU.
4-11 I/O BIDIRECTIONAL DATA BUS: Control, status and
D7-D0 interrupt-vector
information is transferred via this bus.
12- I/O CASCADE LINES: The CAS lines form a private 8259A
CAS0- 13-15 bus to control
CAS2 a multiple 8259A structure. These pins are outputs
for a master 8259A
and inputs for a slave 8259A
16 I/O SLAVE PROGRAM/ENABLE BUFFER: This is a dual
function pin.
SP/EN When in the Buffered Mode it can be used as an
output to control
buffer transceivers (EN). When not in the buffered
 mode it is used as an input to designate a master (SP
= 1) or slave (SP =0).
17 O INTERRUPT: This pin goes high whenever a valid
INT interrupt request is
asserted. It is used to interrupt the CPU, thus it is
connected to the CPU's interrupt pin.
IR0-R7 18-25 I INTERRUPT REQUESTS: Asynchronous inputs. An
interrupt request
is executed by raising an IR input (low to high), and
holding it high until
it is acknowledged (Edge Triggered Mode), or just by
a high level on an
IR input (Level Triggered Mode).
INTA 26 I INTERRUPT ACKNOWLEDGE: This pin is used to
enable 8259A
interrupt-vector data onto the data bus by a
sequence of interrupt acknowledge pulses issued by
the CPU

8259A Programmable Interrupt Controller

A single 8259A connected in the 8086.
The 8259A is decoded at I/O ports 0400H and 0410H.
The SP/EN pin is pulled high to indicate that it is the master node.
8259 A requires 4 wait states for it to function efficiently.
The XT/PC style computers use a single 8259A controller at interrupts vectors 08-0FH

An 8259 interfaced with 8086 microprocessor

Cascading multiple 8259As

This is similar to the connection of a single 8259 with 8086, but here multiple
8259s are connected to an single 8086 .
Two 8259As connected to the microprocessor in a way that is often found in the ATX style computer, which
has two 8259As for interrupts.
The XT or PC style computers use a single 8259A controller at interrupt vectors 08H-0FH.
The ATX computers uses interrupts vector 0AH as a cascade input from a second 8259A located at vectors
70H through 77H.
The I/O ports used for U1 are 0300H and 0302H the master and vectors 70H and 77H and I/O ports 0304H
and 0306H for U2.
Data bus buffers are used to illustrate the use of the SP/EN pin on the 8259A.
These buffers are used in large systems that have many devices connected to their data bus
connections.

Cascading multiple 8259As with 8086

Conclusion

This pin 8259 thus mainly finds its advantage as an controller which can be used without any
additional hardware, to accept up to 64 bit interrupt requests.