JAYPEE UNIVERSITY OF ENGINEERING & TECHNOLOGY

A.B. ROAD, P.B. No. 1, RAGHOGARH, DIST: GUNA (M.P.) INDIA.

Phone : 07544 267051, 267310 - 14 Fax : 07544 267011
Website: www.juet.ac.in

COURSE: MICROPROCESSOR & CONTROLLERS (14B11EC415)

TUTORIAL: 01
TOPIC: REVIEW OF DIGITAL ELECTRONICS
1 Convert the following binary numbers to hexadecimal :
(a) 1011011(b) 10111010(c) 0.10010011(d) 101.00101

[Ans. (a) 5B; (b) BA; (c) 0.93; (d) 5.28]

2 Convert the following hexadecimal numbers to binary :

(a) 89 (b) AB2 (c) 2DE.3 (d) AB3.23

[Ans. (a) 10001001; (b) 101010110010; (c) 1011011110.0011; (d) 101010110011.00100011]

3 Convert the following hexadecimal numbers to decimal :

(a) 20 (b) AD9 (c) 9.C (d) 9.3B

[Ans. (a) 32; (b) 2777; (c) 9.75; (d) 9.2304688]

4 Convert the following decimal numbers to hexadecimal :

(a) 18 (b) 518 (c) 0.54 (d) 5.89

[Ans. (a) 12; (b) 206; (c) 0.8A3D7…; (d) 5.E3D70]

5 Construct a 4-to-16 line decoder with five 2-to -4 line decoder with enable.

6 Construct 16 x 1 multiplexer with two 8 x 1 and one 2 x 1 multiplexer.

7 Construct 16 x 1 multiplexer with two 8 x 1 and OR gate.

8 Implement the following Boolean expression using:

F(A,B,C,D) = π(5,6,7,10,11,12,13,14)
(a) 16 x 1 Multiplexer (b) 8 x 1 Multiplexer (connect B, C, D input to the selection line of MUX)
and NOT gates only.
(c) 4 x 1 Multiplexer (connect A and C input to the selection lines of MUX) and external gates.
(d) 2 x 1 Multiplexer and NOT gates only.
9 Draw the logic diagram of 3x8 decoder with enable low input using
(a) Basic gates (b) NAND gates.
10. Draw the logic diagram of 8x1 multiplexer using (a) basic gates (b) NAND gates.