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Chapter 4. Circuit Characterization and Performance Estimation
Chapter 4. Circuit Characterization and Performance Estimation
• 4.1 introduction.
– Each layer of transistor-forming material has both a resistance and a capacitance that are fundamental
components in estimating the performance of a circuit or a system. (It also has inductance but insignificant
for most on-chip circuit.)
– According to the above formula, the two metal slabs shown in Figure 4.1 have the same resistance.
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-3
– Table 4.1 shows typical sheet resistances for 0.54m to 1.04m MOS process
– Note that for metal having a given thickness, the resistivity is known, while for ploy and diffusion the
resistivities are significantly influenced by the concentration density of the imparities.
– From the voltage-current characteristic of an MOS transistor, the channel resistance in the linear region
L 1
can be approximated as Rc = k ( ) , where k = derived from equation (2.14), 1000
W µC ox(Vgs − Vt )
< k < 30000 Ω/square for n- and p-channel devices.
– Since the mobility of the majority carriers decreases with the increase of temperature, the channel
resistance is increased by approximately 0.25% per oC for temperature above 25 oC.
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-4
– Figure 4.2(b) shows some shapes that are commonly encountered in practice.
– Table 4.2 represents the results of a study to calculate the resistance of the shapes shown in Figure 4.2(b)
for different dimension ratio.
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-5
– Figure 4.5 shows a circuit model comprising parasitic copacitances and the transistor. The total gate
capacitance is given by Cg = Cgb + Cgs + Cgd.
1. Off region, where Vgs < Vt, no channel exists, hence Cgs = Cgd =0. So Cg = Cgb.
– The behavior of the gate capacitance is shown in Table 4.3 where ε = ε O ε SiO2
– Figure 4.6 (a) shows the Cgs and Cgd of a long channel n-transistor (W = 49.2 µ m, L=4.5 µ m).
– Figure 4.6 (b) shows the Cgs and Cgd of a short channel device (L=0.75 µ m). Note that Cgd is finite, i.e., Cgd
> 0. This is due to channel side fringing fields between the gate and drain.
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-11
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-12
– For the purpose of delay calculation, the gate capacitance can be approximated by
ε oε SiO 2 ε ε
C g = Cox A = A, where Cox = o SiO 2 is the “thin-oxide” capacitance per unit area.
t ox t ox
3.9*8.854*10 −14
– With a thin-oxide thickness ( tox ) in the order of 100 → 200Å, Cox =
( 100 → 200 )*10 −8
= 35 →17*10-4 pF/ µ m2.
– The gate capacitance for the case shown in Figure 4.7 for λ = 0.5 µ m, W = 2 µ m and L = 1 µ m and
– Table 4.4 shows typical values of diffusion capacitances for both n- and p-channel devices.
– Note that the above simple capacitance calculations assume zero DC bias across the junction. However,
both Cja and Cjb are functions of junction voltage Vj due to dependence of depletion layer thickness on Vj.
Vj
Thus the junction capacitance is C j = C jo (1 − ) −m ,
Vb
m = a constant dependent on the distribution of impurities. Effective value ranges from 0.3 ~ 0.5.
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-15
• AS = source area,
• AD = drain area,
• PS = source periphery,
• PD = drain periphery.
• .MODEL signals the beginning of MOSFET model
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-16
– From these data, Cg(intrinsic) = W * L * Cox = 4*1*17*10-4 pF = 0.0068pF. Cox is derived form TOX =
200E-8.
– Extrinsic values of Cgso, Cgdo and Cgbo are added to Cgs, Cgd and Cgb to consider the fringing field from gate
terminal . They are specified in SPICE MOSFET Model by CGSO, CGDO and CGBO.
– Cgbo occurs due to the polysilcon ( gate ) extension beyond the channel. Thus Cgbo = CGSO * L * 2.
– Cgso and Cgdo represent the gate source/drain capacitance due to overlap in the physical structure of the
transistor. Thus, Cgso = CGSO * W and Cgdo = CGDO * W.
Cj drain = [15*10-12*2*10-4*(1+2.5/0.7)-0.5]+[11.5*10--6*4*10--10*(1+2.5/0.7)-0.3]F
– The capacitance of the middle layer (conductor of interest ) is divided into three components.
– Empirical formulas to compute these capacitance values are given in Weste text book.
– A long wire can be represented in terms of several RC sections, as shown in Figure 4.15.
dV j V j −1 − V j V j − V j +1
– The response a node Vj with respect to time is given by C = ( I j −1 − I j ) = − ,
dt R R
when expressed as a differential form: rc dV = d V2
2
dt dx
where x = distance from input
– The solution for the propagation of a voltage step along a wire of length x shows that the rise/fall delay
tx = k x2 , where k is a constatnt.
RCn(n + 1)
– Alternatively, a discrete analysis yields a signal delay of t n = 0.7 * , where n is the number of
2
sections. As n becomes very large, t l = 0.7 rcl 2
2
– Figure 4.16 shows an example of using the above formula to insert a buffer on a long wire
• without a buffer, the propagation delay tp = 0.7 * 20 * 4 *10-4 * 20002 /2= 112ns
• with a buffer on the middle, tp = (2 * 0.7 * 20 * 4 *10-4 * 10002 )/2+ tbuf =66ns + tbuf
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-23
– Note that the above calculation considers only propagating a voltage step signal along the wire.
– A model for the distributed RC delay, which takes driver and receiver loading into account is shown in
Figure 4.17, where
– To model a wire as a simple capacitive load, the wire‘s RC delay τ w and gate delay τ g must satisfy:
1 2τ g
τ w << τ g ⇒ rcl 2 << τ g ⇒ l <<
2 rc
– For example, assume τg = 200ps and for a minimu-width aluminum wire
2* 0.2*10 −9
l << ≈ 16000 λ
0.05 *30* 10 −18
λ λ
where r = 0.05 Ω / λ
c = 30 * 10-18 F/ λ
– Table 4.7 shows the maximum interconect length for a typical CMOS proces in terms of λ such that a wire
can be modeled as a simple capacitive load. This table assumes gate delays of the order of 100ps to 500 ps.
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-28
• 4.4 Inductance
– On-chip inductances are small, but bond-wire inductances are large enough to cause troubles for I/O
dI
circuits(voltage spike dV = L ).
dt
• For an on-chip conductor whose inductance is L = µ ln ( 8h + w ) .
2π w 4h
where w = the width of the conductor
h = the height above the substrate.
dVout 1 2
– During tf2, the n-device is non-saturated, thus C L = − β n ((VDD − Vtn )Vout − V. out )
dt 2
CL
Solving this equation, we obtain t f 2 = ln(19 − 20n) , where n = Vtn
β nVDD (1 − n) VDD
2C L (n − 0.1 ) 1
– tf = tf1 + tf 2 = + ln ( 19 − 20n) (4.37)
β nVDD( 1 − n) ( 1 − n) 2
CL
that is, t f ≈ k × where k = 3~4.
β nVDD
1
• tf ∝ CL, tf ∝ 1/VDD and tf ∝ .
βn
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-32
– In most CMOS circuits, the delay of a single gate is dominated by the output rise and full times. It is
tr t
approximated by t dr = and t df = f .
2 2
t + t dr t r + t f
– The average gate delay for rising and falling transition is t av = df = .
2 4
– Figure 4.20 illustrates a SPICE simulation of a step input applied to an inverter driving a capacitive load.
With Vtn = .767V , Vtp = −.938V , β = 4.04 × 10 −4 ,β = 3.48 × 10 −4 , VDD = 5.0V , C L = 0.5 pF.
n p
CL AN
– Alternatively, the output fall delay time can be approximated by t df = AN (i.e., Rn = ). AN is a
βn βn
1 2n 2(1 − n) − VO
process-specific constant and derived as AN = + ln( )
VDD (1 − n) 1 − n VO
where n = Vtn and VO = Vout .
VDD VDD
C 1 − 2p 2(1 + p ) − VO Vtp
Similarly, t dr = Ap L A
( E.Q. 4.47) and p = 1 + p + ln where p = <0 .
β V DD (1 + p ) V O V DD
p
βp 3.48 × 10 −4
Ap = t dr − spice = 0.52 × 10 −9 × = 0.36 (0.31 calc)
CL 0.5 × 10 −12
βn 4.04 × 10 −4
AN = t df −spice = 0.45 × 10 × −9
−12
= 0.36 (0.29 calc)
CL 0.5 × 10
Note that the values of tdr-spice and tdf-spice are obtained from SPICE simulation.
– For example, the equivalent inverter for the 3-input NAND gate shown in Figure 4.21 has the effective β
1
of the n-transistor as β neff = 1 1 1
+ +
β n1 β n2 β n3
– For β n1 = β n 2 = β n 3 , β = β n
neff
3
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-36
– For the pull-up case, only one p-transistor has to turn on to raise the output. Thus, β peff = β p.
CL CL tr
For β p = 0.3β n , t r = k , tf = k . Thus ≈1 .
0.3β nVDD β n
t f
VDD
3
– In general, the fall time is mtf for m n-transistors in series; the rise time for m p-transistor in series is mtr.
– The fall (rise) time for a parallel connection of n(p)-transistors is tf/m (tr/m) for m transistors in parallel, if
all the transistors are turned on simultaneously.
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-37
– Figure 4.23 shows the influence of input waveform on the delay time of an inverter based on SPICE
simulation.The results are tabulated in Table 4.8.
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-38
– The following modification to the output rising delay is made to consider the input waveform slope:
tinput − fall Vtp
t dr = t dr −step + (1 − 2 p ) , p =
<0
6 VDD
where tdr-step = the output rising delay due to a step input calculated in EQ. 4.47 .
– An effect known as bootstrapping can also modify the effective input capacitance of a logic gate.
– As shown in Figure 4.24(a), in the case where the input is rising (that is, the output is high), the effective
input capacitance is Cgs+Cgd.When the output starts to fall, the voltage across Cgd increases, requiring the
input to supply more current to charge Cgd. This effect is seen in Figure 4.24(b).
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-40
– A variety of timing models have developed to estimate the delay of logic gates:
• Simple RC model: the total resistance of pull-up or pull-down path is calculated and all the
capacitance of nodes are lumped onto the output of the gate.
For the example shown in Figure 4.26.,
t df = ∑ R pulldown ∗ ∑ C pulldown − path = ( RN 1 + RN 2 + RN 3 + RN 4 ) ∗ (Cout + Cab + Cbc + Ccd )
, while for the rise delay tdr = Rp4 * Cout. This is a pessimistic model.
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-41
• 4.5.4.4 Macromodeling
– To derive a set of accurate formulae to calculate gate capacitance and logic gate behavior based on the
device equation.
– Figure 4.28 shows a typical model along with the timing model, where tswin is the input waveform, tswout is
the output waveform, Cin is the input capacitance, and CL is the output capacitance.
– Another commonly used approach in ASIC community treats logic gates as simple delay elements. Each
gate type is simulated with a circuit simulator to derive an equation to compute the delay of a particular
gate: td = tinternal + k* toutput, where tinternal is a fixed delay when no load is attached; k is the output loading;
toutput is the output delay per output loading.
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-43
– Figure 4.29 shows a typical SPICE circuit used to calibrate delay equation.
– Thus for the gate shown in Figure 4.29, tdr = (0.255 + k * 2.12) ns, tdf = (0.42 +k *3.82) ns
– .
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-44
– ∆Vt ∝ r Vsb , where r is a constant, Vsb is the voltage between source and substrate, and ∆Vt is the
change in threshold voltage.
– For the example shown in Figure 4.30(a), the n-transistor at the output will switch slower if the source
potential of this transistor is not the same as the substrate.
– In the upper NAND gate the lower transistors are initially turned on while transistor N4A is turned off. The
result is seen in Figure 4.30(b) in the form of waveform CD when the input on N4A rises.
– In the lower NAND gate, the upper transistors are turned on initially, while transistor N1B is turned off.
(Effectively, the Vsb of the upper transistors is not equal to zero). The result is seen in Figure 4.30(b) when
N1B turns on, which indicates the output transition lags behind 0.4 ns.
– For example, as for the circuit shown in Figure 4.31(a), with Wp = 2Wn ,
R
tinv− pair ∝ t fall + t rise ∝ R3Ceq + 2 3Ceq = 3RCeq + 3RCeq = 6 RCeq
2 ,
where R is the effective “ON” resistance of a unit-sized n-transistor (W=2, L=1), and Ceq = Cg+Cd is the
capacitance of a unit-sized gate and drain region. As for the case shown in Figure 4.31(b) with Wp = Wn,
– Also note that changes in the β ratio affect the inverter logic threshold voltage Vinv, which directly
influences the delay of output response. From equation (2.2),
βn
VDD + Vtp + Vtn
βp
Vinv =
βn
1+
βp
– Considering the circuit shown in Figure 4.33, inv-1 is a minimum-sized inverter driving inv-2, which is a
times the size of inv-1. Similarly, the size of inv-3 is a times the size of inv-2 (that is, inv-3 is a2 the size of
inv-1).
– The delay through each stage is atd, where td is the average delay of a minimum-sized inverter driving
another minimum-sized inverter. Hence the delay through n stages is natd. If the ratio of the load
capacitance to the capacitance of a minimum-sized inverter is R=CL / Cg , then R = an. Hence ln(R)=nln(a).
ln( R)
Thus, Total delay = nat d = at d .
ln(a)
– The variable part of the above equation, normalized to e, is graphed in Figure 4.33(b). The graph shows
when a = 2.7 = e would minimize the total delay.
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-49
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-50
– The leakage current between diffusion and substrate can be explained by the model shown in Figure 3.35.
The diodes in the model are reverse-biased and the leakage current is described by diode equation.
io = is (e qV kT
− 1)
T = temperature
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-52
– Short circuit dissipation is due to existence of a direct path from VDD to VSS when the output changes either
from 1 to 0 or 0 to 1.
– Short circuit dissipation depends on the input rise/fall time, the load capacitance and gate design.
– Fig 4.36 depicts a scenario about how output loading could influence the short circuit current.
– The average dynamic power Pd dissipated during switching for a square-wave input, Vin, having a
repetition frequency of fp=1/tp is given by
1 tp 1 t
Pd = ∫02 in (t )Vout dt + ∫t pp i p (t )(VDD − Vout )dt
tp tp 2
C L dVout
For a step input and with in (t ) = dt
,
2
C V C 0 CV
Pd = L ∫0 DD Vout dVout + L ∫VDD (VDD − Vout )d (VDD − Vout ) = L DD = C LVDD f p
2
tp tp tp
– Dynamic power dissipation can be limited by reducing supply voltage, output capacitance and the
switching frequency.
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-54
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-55
Pd = ,
tp
where percentage-activity is a ratio between the estimated number of switchings and the number of
clock cycles during a certain period of time.
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-56
transistor
network Vout
Ig Rg
VSS-inv = Ig*Rg
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-58
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-59
– For a successful sampling, the resultant voltage VR (not shown) should be correctly reflect the state of the
if Vb=VDD (the bus is in state ‘1’), and Vb>>Vs , then VR=VDD[Cb/(Cb+Cs)]. For a successful sampling,
– Example:
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-61
Application Temperature
o
Min ( C) Max(oC)
Commercial 0 70
Industrial -40 85
Military -55 125
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-62
– For example, if Qja = 30 oC/watt, Pd = 1 watt, and Ta = 85 oC, then Tj = 115 oC.
– The variations in device performance can be caused by variations in doping density, implant dose, and
variations in the width and thickness of active diffusion and oxide layers and passive conductors.
– When considering the influence of process variation on the transistor speed, the following terms are used:
• nominal(typical)
• fast
• slow
– There are four types of boundary conditions for two types of transistors:
• Fast-n and fast-p
• Fast-n and slow-p
• Slow-n and fast-p
• Slow-n and slow-p
– If the gains of the p- and n-transistors track but the threshold voltage is not, the following process corners
can be observed:
• Slow-n and low-Vtp
• Low-Vtn and slow-p
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-64
– The worst-power or high-speed corner: fast-n and fast-p process corner combined with the lowest
operating temperature and the highest operating voltage.
– The worst-speed corner: slow-n and slow-p process corner combined with the highest operating
temperature and the lowest operating voltage.
– The worst-speed corner can be used to check external setup times while the highest speed corner can be
used to check hold time constraints.
– Table 4.11 shows a list of checks performed for a CMOS digital system.
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-65
– The thermal impedance is a measure of the effectiveness with which a package can conduct heat away
from the die.
• 4.11 Yield
– The yield is influenced by such factors as:
• technology
• chip area
• layout
– Yield is defined as Y= (No. of good chips on wafer) / (Total number of chips)
• 4.12 Reliability
– The potential reliability of a CMOS chip:
• “Hot electron” effects
• Electro-migration
• Oxide failure
• Die temperature
• ESD protection.
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-67
– For example, scaling the thickness and width of a conductor byα ,the scaled-line resistance R’ is given by
Lα ρ Lα
R ' = R s '[
]= [ ] = αR,
W α tα W α
where ρ = conductivity
ρ
Rs ' = is sheet resistance of the scaled-line
tα
t = conductor thickness before scaling
– The voltage drop along the scaled-line for a constant field scaling is
I
Vd ' = ( )(αR ) = IR
α
– The line-response time is
C
t s ' = (αR )( ) = RC
α
Chapter 4:Circuit Characterization and Performance Estimation Rung-Bin Lin 4-69
1
– The influence of scaling on interconnect, if the interconnect is scaled by α and the current is increased
α
by , is summarized in Table 4.13.
• 4.14 Summary
– resistance, capacitance, inductance calculations
– delay estimation
– power estimation
– effect of scaling